avalanche83:
Since CAS 1.5 may be the same as CAS 2 (for DDR in A64 setting),
and you have been doing the latency vs timing parameter runs using Everest, could you do another test.
Can you do two runs and compare the latency numbers:
1. 200 MHz 2-2-2-6
2. 300 MHz 3-3-3-9
"If all the timing parameters (in number of cycles) for case A are exactly N times that of case B, and frequency of case A is also N times that of case B, then the latency (in seconds) for both cases would be the same."
latency = (k1 t1 + k2 t2 + k3 t3 + ...) / freq
where
t1, t2, t3, ... are the timing settings,
and k1, k2, k3, ... are the corresponding constants to calculate latency.
E.g.
read_latency ~ (tRCD + 8 tCAS) / freq .... for burst-8 page mode
read_cycle_time ~ (tRCD + tCAS + tRP) / freq
If all the timing settings t1, t2, t3, ... for cases A and B are in the same ratio as freq_A to freq_B,
then latency_A = latency_B
E.g.
200 MHz 2-2-2-6 vs 300 MHz 3-3-3-9, the ratio is 2:3.
Memory frequency and latency tradeoff (post 195)
Gautam said:
...
Btw where have you been hitech? Good to see you back.
I have been around, mostly updating the various posts in the stickies rather than new posting. Like in the past, from TbredB to Barton to various A64 cores, ..., if there are new things/questions that I have to learn, understand and solve (curiosity), I probably will post more, ...
