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running Tualatin on CuMine MB w/o Powerleap
- Thread starter soil
- Start date
- Joined
- Mar 17, 2002
- Location
- Portoroz, Slovenia
@ DSTA :
>And another question: how on earth did this blasted pin N33 become synonimous with BR1 on sub CB0 coppermines? Did anyone ever bother to try one of those with X2? Why the %%§$% does it work with N33 at all? It shouldn't!
on prior to cB0 stepping SMP was disabled !
>but I'd wish the resistance of a BR pin would have been something "special".
NOT necessary!
>Would have been easier to find out if it's not hiding behind one of the various "reserved" pins on Tualatin Celeron.
This is to consider seriously too, but if there is some resistance it means that the pin is connected to the core & NOT non-connected! & there is something also very interesting: the pin AN29 is a BR#0 which is also important for SMP & is the ONLY bidirectional !!! BusReq pin! On Intel datasheet for PIII states, that for uniprocessor use should be terminated to Vss(gnd) with a 10-56ohm resistor !!!!! I think resistors for Tuallie should be greater about 30%, IMHO max 100ohm! That means that we can isolate it & rewire it somewhere else /but where!/, can´t we?
Also on 2cpu.com forum a guy- brokenwallet, gave me also this idea:
>Cover pin X2 and X4 from contacting their sockets. Then connect/wire pin AJ3 to the socket of pin X2; this connects the RESET#2 pin with the RESET#2 socket.
>Then, connect/wire pin X2 to the socket of X4; this should connect pin X2 (BR1) of the tualatin cpu to a socket that has AGTL I/O signal.
This is to consider too...
@ DsK
>I have the MSI 6163 pro rev2, just for ref.
Me too; thanks for confirming that it works on it; so if it does not ot mine, would be definitively not adequate slotket the cause! (I have 2 different generic ppga/Fc-Pga ones, got them few days ago, still waitig for my pair of Tc1.0A next week)..
>And another question: how on earth did this blasted pin N33 become synonimous with BR1 on sub CB0 coppermines? Did anyone ever bother to try one of those with X2? Why the %%§$% does it work with N33 at all? It shouldn't!
on prior to cB0 stepping SMP was disabled !
>but I'd wish the resistance of a BR pin would have been something "special".
NOT necessary!
>Would have been easier to find out if it's not hiding behind one of the various "reserved" pins on Tualatin Celeron.
This is to consider seriously too, but if there is some resistance it means that the pin is connected to the core & NOT non-connected! & there is something also very interesting: the pin AN29 is a BR#0 which is also important for SMP & is the ONLY bidirectional !!! BusReq pin! On Intel datasheet for PIII states, that for uniprocessor use should be terminated to Vss(gnd) with a 10-56ohm resistor !!!!! I think resistors for Tuallie should be greater about 30%, IMHO max 100ohm! That means that we can isolate it & rewire it somewhere else /but where!/, can´t we?
Also on 2cpu.com forum a guy- brokenwallet, gave me also this idea:
>Cover pin X2 and X4 from contacting their sockets. Then connect/wire pin AJ3 to the socket of pin X2; this connects the RESET#2 pin with the RESET#2 socket.
>Then, connect/wire pin X2 to the socket of X4; this should connect pin X2 (BR1) of the tualatin cpu to a socket that has AGTL I/O signal.
This is to consider too...
@ DsK
>I have the MSI 6163 pro rev2, just for ref.
Me too; thanks for confirming that it works on it; so if it does not ot mine, would be definitively not adequate slotket the cause! (I have 2 different generic ppga/Fc-Pga ones, got them few days ago, still waitig for my pair of Tc1.0A next week)..
- Joined
- Nov 29, 2001
- Location
- NRW, Germany
>on prior to cB0 stepping SMP was disabled !
Well, not really. Never was disabled for slot 1 CPUs, and only was undocumented for FCPGA. But let's forget about that N33 business, it's probably specific to that first revision MSI adapter (MS 6905).
>This is to consider seriously too, but if there is some resistance >it means that the pin is connected to the core & NOT non->connected!
Yes, if there's a resistance, at least it must be wired to something.
It just would have been nicer if a BR pin had a special resistance so one could find out if there was one on a given CPU. That's why I measured the BR1 and BR0 from that PPGA Celeron.
If it's not at X2, it can only be on one of the "reserved" pins or, and I fear that is more likely, not connected.
>& there is something also very interesting: the pin AN29 is a >BR#0 which is also important for SMP & is the ONLY >bidirectional !!! BusReq pin!
Hm, yes.
I think the article from Ars Technica I linked to in a previous post was a bit misleading. They started with a Pentium Pro data sheet, those had 4 way MP bus arbitration (that was done a bit differently).
For 2 way, it works like this IMO:
The Northbridge has two BREQ lines. BREQ0 and BREQ1.
On the CPU0 socket, BREQ0 is wired to BR0.
On the CPU1 socket, BREQ0 is wired to BR1.
On the CPU0 socket, BREQ1 is wired to BR1.
On the CPU1 socket, BREQ1 is wired to BR0.
The BR1 pin is only needed during power up configuration. Only function is to tell the CPU that it is either CPU0 or CPU1.
What I'd love to try is if one could get two different CPUs to POST (doubt it would be of much use in an OS after that). Say a Coppermine P3 in Socket 1 and a Coppermine Celeron in Socket 0 (so that it doesn't need BR1).
>On Intel datasheet for PIII states, that for uniprocessor use >should be terminated to Vss(gnd) with a 10-56ohm >resistor !!!!! I think resistors for Tuallie should be >greater >about 30%, IMHO max 100ohm! That means that we can >isolate it & rewire it somewhere else /but where!/, can´t we?
I don't think this has something to do with the BR0/1 story. With Pentium MP systems, the CPUs all sit on the same bus and need to have proper termination depending on what CPUs sit there and how many there are (bit like a SCSI chain).
Mobo (and Slotket) should take care of this already.
Well, not really. Never was disabled for slot 1 CPUs, and only was undocumented for FCPGA. But let's forget about that N33 business, it's probably specific to that first revision MSI adapter (MS 6905).
>This is to consider seriously too, but if there is some resistance >it means that the pin is connected to the core & NOT non->connected!
Yes, if there's a resistance, at least it must be wired to something.
It just would have been nicer if a BR pin had a special resistance so one could find out if there was one on a given CPU. That's why I measured the BR1 and BR0 from that PPGA Celeron.
If it's not at X2, it can only be on one of the "reserved" pins or, and I fear that is more likely, not connected.
>& there is something also very interesting: the pin AN29 is a >BR#0 which is also important for SMP & is the ONLY >bidirectional !!! BusReq pin!
Hm, yes.
I think the article from Ars Technica I linked to in a previous post was a bit misleading. They started with a Pentium Pro data sheet, those had 4 way MP bus arbitration (that was done a bit differently).
For 2 way, it works like this IMO:
The Northbridge has two BREQ lines. BREQ0 and BREQ1.
On the CPU0 socket, BREQ0 is wired to BR0.
On the CPU1 socket, BREQ0 is wired to BR1.
On the CPU0 socket, BREQ1 is wired to BR1.
On the CPU1 socket, BREQ1 is wired to BR0.
The BR1 pin is only needed during power up configuration. Only function is to tell the CPU that it is either CPU0 or CPU1.
What I'd love to try is if one could get two different CPUs to POST (doubt it would be of much use in an OS after that). Say a Coppermine P3 in Socket 1 and a Coppermine Celeron in Socket 0 (so that it doesn't need BR1).
>On Intel datasheet for PIII states, that for uniprocessor use >should be terminated to Vss(gnd) with a 10-56ohm >resistor !!!!! I think resistors for Tuallie should be >greater >about 30%, IMHO max 100ohm! That means that we can >isolate it & rewire it somewhere else /but where!/, can´t we?
I don't think this has something to do with the BR0/1 story. With Pentium MP systems, the CPUs all sit on the same bus and need to have proper termination depending on what CPUs sit there and how many there are (bit like a SCSI chain).
Mobo (and Slotket) should take care of this already.
- Joined
- Jan 23, 2001
On a similar note, I'm working on getting my old p3 700 to work on a PPGA 810 motherboard. I removed AM2 and jumped AH4 and X4. So far, it posts, and with correct Vcore, but I cant get into windows. I may have to mod the socket ...there are two pins I have to ground with resistors. I'll post results as they happen.
- Joined
- Mar 23, 2002
- Location
- Oslo, Norway
Re: What about P3B-F and Soltek SL-02A++ ?
I'm testing a Celeron 1.1A @ 1364MHz (124MHz bus and 1.65V) on an Asus P3B-F with an Asus S370-DL 1.02 adapter. I have modded the latest beta-bios for it to get the Tualatin microcode.Slyde said:Hi everyone,
I'm currently running a Cel900@1200 and i'm very interested in getting a 1.1@1466 CelT
I was wondering whether someone was able to run a Cel Tualatin on a Asus P3B-F motherboard with a Soltek SL-02A++ (don't seem to be very common in US !). I also got an Asus Slotket so i'll be happy if the P3B-F is ok.
- Joined
- Mar 23, 2002
- Location
- Oslo, Norway
Re: Re: Re: What about P3B-F and Soltek SL-02A++ ?
. I dont think the microcode has anything to do with what the processor is identifyed as, but after i modded the bios i stopped getting unsupported cpu and gained stability.
My CPU is identified as Pentium II 1364MHzPiT said:
And you were succesfull or not ?
Because I've taken CPUCode from ST6 and then from VH6T and modded my BIOS and my MoBo still can't identify my CeleryT
. I dont think the microcode has anything to do with what the processor is identifyed as, but after i modded the bios i stopped getting unsupported cpu and gained stability.
Last edited:
- Joined
- Mar 17, 2002
- Location
- Portoroz, Slovenia
Re: Re: Re: Re: What about P3B-F and Soltek SL-02A++ ?
@ DSTA :
<What I'd love to try is if one could get two different CPUs to POST (doubt it would be of much use in an OS after that). Say a Coppermine P3 in Socket 1 and a Coppermine Celeron in Socket 0 (so that it doesn't need BR1).
With that Celly IMHO could not work even if it posts.
Time ago AIRcl I read somewhere on the Net that some Russian testing a bunch of different dual mobos succided with one PIII600E&PIII800EB cB0 putted together on a Epox EP-d3va & it worked!!! Sure the lower one was obviously OC-ed, but that was the only board that could do that! No one other! But this could be also a hoax info!
But here are also some good news: I compared the datasheets today between SMP capable PIII-S & so called by Intel non-SMP capable Tuallie: the result extracted from Signal listing chart: the ONLY DIFFERENCE between the two of them is, believe or not, the BR1 pin /agtli/o = pin X2 which for Tuallie is marked as Reserved! What the hell!
So, can someone actually tell me if there is some resistance to some Vss or VccCore pins on this pin on exactly that CeleronTualatin CPU that we can actually see if is there connected to something or isolated???
I am more & more convinced that someone will sooner or later make Tuallies work SMP, do not know where, when or how; but IMHO Intel just imposted manufacturers of mobos to implement in Bios proper recognition of CPU to not let them work in dual already time ago with the not commercialised desktop PIIItualatin wersion, which now became commercialised as Celeron Tualatin! The same did AMD for their AthlonXP, but was already found out how to convince those mobos to recognise them like MP
(cpu bridges mod) & run them normally!
Could somebody else study further datasheets to make a final mod to some standard dual fcpga mobo that we can succeed? More ideas needed!
@ DSTA :
<What I'd love to try is if one could get two different CPUs to POST (doubt it would be of much use in an OS after that). Say a Coppermine P3 in Socket 1 and a Coppermine Celeron in Socket 0 (so that it doesn't need BR1).
With that Celly IMHO could not work even if it posts.
Time ago AIRcl I read somewhere on the Net that some Russian testing a bunch of different dual mobos succided with one PIII600E&PIII800EB cB0 putted together on a Epox EP-d3va & it worked!!! Sure the lower one was obviously OC-ed, but that was the only board that could do that! No one other! But this could be also a hoax info!
But here are also some good news: I compared the datasheets today between SMP capable PIII-S & so called by Intel non-SMP capable Tuallie: the result extracted from Signal listing chart: the ONLY DIFFERENCE between the two of them is, believe or not, the BR1 pin /agtli/o = pin X2 which for Tuallie is marked as Reserved! What the hell!
So, can someone actually tell me if there is some resistance to some Vss or VccCore pins on this pin on exactly that CeleronTualatin CPU that we can actually see if is there connected to something or isolated???
I am more & more convinced that someone will sooner or later make Tuallies work SMP, do not know where, when or how; but IMHO Intel just imposted manufacturers of mobos to implement in Bios proper recognition of CPU to not let them work in dual already time ago with the not commercialised desktop PIIItualatin wersion, which now became commercialised as Celeron Tualatin! The same did AMD for their AthlonXP, but was already found out how to convince those mobos to recognise them like MP
(cpu bridges mod) & run them normally!
Could somebody else study further datasheets to make a final mod to some standard dual fcpga mobo that we can succeed? More ideas needed!
Re: Re: Re: Re: What about P3B-F and Soltek SL-02A++ ?
2 Kamerat:
Hmm.
Good for you.
My MoBo identifies the CPU as P!!! 333 MHz and at 11*133 as P!!! 693 MHz
And this MoBo supports even multipliers 12.
Can anybody tell me, what should I do, to get correct frequency from BIOS ?
2 Kamerat:
Hmm.
Good for you.
My MoBo identifies the CPU as P!!! 333 MHz and at 11*133 as P!!! 693 MHz
And this MoBo supports even multipliers 12.
Can anybody tell me, what should I do, to get correct frequency from BIOS ?
Re: Re: Re: Re: Re: What about P3B-F and Soltek SL-02A++ ?
edit yourself a bios with tualitin microcode in it
PiT said:2 Kamerat:
Hmm.
Good for you.
My MoBo identifies the CPU as P!!! 333 MHz and at 11*133 as P!!! 693 MHz
And this MoBo supports even multipliers 12.
Can anybody tell me, what should I do, to get correct frequency from BIOS ?
edit yourself a bios with tualitin microcode in it
- Joined
- Feb 27, 2002
- Location
- Genova,Old World
have a look in martinus onofficial site and his guide
on modify the bios
on modify the bios
- Joined
- Feb 27, 2002
- Location
- Genova,Old World
on your abit Bx133 u could use the same modded bios
i did for my BX133
It has an updated Cpucode and HPT 2.31 bios
http://digilander.iol.it/grandecigno/files/Ber_72H1.zip
i did for my BX133
It has an updated Cpucode and HPT 2.31 bios
http://digilander.iol.it/grandecigno/files/Ber_72H1.zip
No.belinassu said:on your abit Bx133 u could use the same modded bios
i did for my BX133
It has an updated Cpucode and HPT 2.31 bios
http://digilander.iol.it/grandecigno/files/Ber_72H1.zip
I've tried your BIOS and it still says "Pentium III 693 MHz" .
Any ideas???
Last edited:
- Joined
- Aug 21, 2001
- Location
- under a rock
PiT said:
I have the same problem as you. For some reason, it reported the speed of the 1.0A correctly but not for the 1.1A. I too am using belinassu's modded bios.
- Joined
- Feb 27, 2002
- Location
- Genova,Old World
strange , i grabbed the cpu code from a ST6R bios
supporting also 1.1A celeron.....
supporting also 1.1A celeron.....
- Joined
- Mar 17, 2002
- Location
- Portoroz, Slovenia
Info (DANGER?) to all guys using mod for wiring AK4 to AK26 pin directly: if you use conductive paint to do that like bellinassu did /it has some resistance, but not so important for Cmos levels/, should be ok, but if you use a wire, maybe not! In datasheet for PIII-S states that Pwrgd is 1,8V tolerant, but VttPwrgd NOT! (only 1,5v tolerant!), so IMHO maybe would be better to wire those pins together not directly but thru a resistor of approx. 1Kohm to prevent long term damage of Tuallie & later instabilities while OC-ing !!! Is to think about!
- Joined
- Aug 9, 2001
- Location
- A galaxy far, far away
I got my Cel 1.1 to post and run on an Asus P3C-2000 MB.
This is the MB with the memory translator hub. It doesnt have good memory bandwidth, but hey, cant complain for free.
Anyhow, its mounted on an Asus S370-DL slotket, jumpers set to 1.60 volts.
I have blocked off the 3 pins, but have not done the AK4/AK26 connection, or the voltage mods on the Vid pins.
Strange thing though, I can boot up and load windows with the FSB set to 153, and the multiplier set to 8x in the bios. Now, I know that I cant change the multiplier on an Intel chip.
I do get an invalid CPU ID error message when booting up.
What I dont understand is that supposedly running at 1224Mhz, it gets lower timings than the original P3-667 Slot1 CPU that was in there.
Remember the MB I am using, with a FSB of 153, the memory is running at 117.
Do I need to alter the bios microcode, to see any improvement?
Or should I go get a good 'ol BX board, and toss this poor excuse of a MB?
PS. I ran Seti@Home for 6 hours with no problems. I cant go any higher, due to the MTH on the MB not being able to withstand any higher memory speed.
This is the MB with the memory translator hub. It doesnt have good memory bandwidth, but hey, cant complain for free.
Anyhow, its mounted on an Asus S370-DL slotket, jumpers set to 1.60 volts.
I have blocked off the 3 pins, but have not done the AK4/AK26 connection, or the voltage mods on the Vid pins.
Strange thing though, I can boot up and load windows with the FSB set to 153, and the multiplier set to 8x in the bios. Now, I know that I cant change the multiplier on an Intel chip.
I do get an invalid CPU ID error message when booting up.
What I dont understand is that supposedly running at 1224Mhz, it gets lower timings than the original P3-667 Slot1 CPU that was in there.
Remember the MB I am using, with a FSB of 153, the memory is running at 117.
Do I need to alter the bios microcode, to see any improvement?
Or should I go get a good 'ol BX board, and toss this poor excuse of a MB?
PS. I ran Seti@Home for 6 hours with no problems. I cant go any higher, due to the MTH on the MB not being able to withstand any higher memory speed.
- Joined
- Mar 23, 2002
- Location
- Oslo, Norway
That is because you don't have the Tualatin microcode I think.Wookie8662 said: