X299 motherboards

[DaveB]

Hi, I need help to boot my newly bought ASUS X299 E motherboard with 7740 processor & Corsair DDR4 ECC 32 GB RAM with ASUS Graphics card GEFORCE 1080. While booting, nothing appears in my 4 k monitor & the code display stops after A0. Can you pls help me to go to the boot screen to activate use of M.2. I have not installed any HDD/SSD on the board other than M.2 slot.

From the motherboard specifications:

ntel® Core™ X-series Processors (6-core above)
8 x DIMM, Max. 128GB, DDR4 4133(O.C.)/4000(O.C.)/3866(O.C.)/3733(O.C.)/3600(O.C.)/3466(O.C.)/3400(O.C.)/3333(O.C.)/3300(O.C.)/3200(O.C.)/2800(O.C.)/2666/2400/2133 MHz Non-ECC, Un-buffered Memory
Intel® Core™ X-series Processors (4-core)
4 x DIMM, Max. 64GB, DDR4 4133(O.C.)/4000(O.C.)/3866(O.C.)/3733(O.C.)/3600(O.C.)/3466(O.C.)/3400(O.C.)/3333(O.C.)/3300(O.C.)/3200(O.C.)/2800(O.C.)/2666/2400/2133 MHz Non-ECC, Un-buffered Memory
** Refer to www.asus.com for the Memory QVL (Qualified Vendors Lists).
* Hyper DIMM support is subject to the physical characteristics of individual CPUs.

 

[batboy]

The 7740X has 4 cores and any CPU with less than 6 cores can only run dual channel RAM, not quad channel. You have to install the RAM DIMMs exactly like the manual shows (it'll have 2 diagrams depending on how many cores your CPU has). When I was building my new X299 system, I got mixed up on RAM configuration too.

 

[Woomack]

ASUS QVL list is a joke. It's impossible to have the same memory support on 4 and 6+ cores. Also how they managed to test couple of 4133+ memory kits at 4133 when max in OC rankings on SL-X is 4000 for quick AIDA64 test and it's not even on ASUS board. ASUS made the same list for every single X299 board even though in their X299 guide max memory clock in quad channel is 3600 and on the product page is support for 4133.
I guess the same is with ECC. In theory any ECC non-registered should work but it's not guaranteed that ECC will be activated. ECC registered modules probably won't work if there is no full support ( IMC+BIOS ). These boards are still on early BIOS releases so hard to say if all is working.
Btw. there is new BIOS for TUF Mk. 2 but I had no time to check it yet.

 

[mackerel]

Btw. there is new BIOS for TUF Mk. 2 but I had no time to check it yet.

I'm still on original bios... I'll probably throw that one on tomorrow evening as I'm in a compute challenge at the moment.

 

[mackerel]

Just put the new bios on. After restoring my 4.3 AVX overclock, I can't say there is anything noticeably different. I haven't tried pushing further yet. Playing with adaptive voltage is still on my "to do" list as I do want to use different voltage settings for AVX and non-AVX. Someone had asked about cache vs uncore voltage previously. I do note they're separate options in the bios. Don't recall if that was the case previously.

 

[batboy]

I flashed to BIOS version 0702 the other day. That's the latest, right? Mine had version 0402 when I took it out of the box. Think version 0503 was the one in between. I heard few complaints about 0503. The only thing I noticed different was a new temp (VRM) was unlocked.

 

[Johan45]

Just put the new bios on. After restoring my 4.3 AVX overclock, I can't say there is anything noticeably different. I haven't tried pushing further yet. Playing with adaptive voltage is still on my "to do" list as I do want to use different voltage settings for AVX and non-AVX. Someone had asked about cache vs uncore voltage previously. I do note they're separate options in the bios. Don't recall if that was the case previously.

I've been playing with this new platform 7900x was good with AVX and the new 29.1 but I have a 7820x on the bench now and it's really having issues with it. I just wanted to say I have been working with the AVX offset in bios and it doe work. You dont need different voltage just figure out which clocks work with the same voltage. This CPU runs AVX at 4.4 but 4.8 for everything else so I set a -4 offset for AVX. Watching in SW I see it drop from 4.8 to 4.4 when I run P95 but CB15 runs at 4.8 All with the same 1.25V setting for the core this was on MSI Gaming M7

 

[mackerel]

My current separately tested configuration is 4.3 GHz 1.10v for AVX, and 4.8 GHz 1.25v for everything else. I don't want to increase voltage for AVX as that is the run condition I want to optimise for as it will be the bulk of the CPU cycles on that system. I don't mind over-volting non-AVX as that is far less important. I've heard somewhere offset voltage might offer something like that. If I'm unable to do that, I will instead just find out what the best non-AVX I can get for 1.10v. I really don't want to run AVX at the higher voltage. From my notes I never tested non-AVX at 1.10v, and 1.20v only got me 4.6 so it seems hardly worth the effort over 4.3 1.10v.

 

[Byórðæįr]

I get the feeling that the raid one being mirroring is likely to prevent someone from sticking that in someone else's computer turn it on to build a mirror array then turn it off to walk off with a copy of the data on the array. Raid zero being stripping it would write to one than the other and you would need to be able to log in to make sure that you could copy the data via the interface. The design industry deals with expensive dongles like that all the time. The costs get added in to the overhead. Every time I think of putting my operating system on something that has a limited number of writes I look at a book with an sd card I have you can not read or write the data to. It was the main data sd card for my phone which I used like a personal Assistant. So I back up my hard drives every six months to a new drive and put the old drive in storage but I use flash drives as swap memory, game directories or anything that needs to be fast but the data that is important comes from another location. Like my video games the save directory that is on a hard drive for games, my cloud saves back up, but games like wow all the data is on their server so that could sit on flash memory and does cause updates but benefits from the speed. maya's swap file space could be on one and the programs on another. The actual work folders and the assets folders those are tape drives or platters. My music data platters and tape drive. My current setup has most of the hard drives sitting in a pile right now but I am upgrading in October.

Short version your operating system should be on a drive that is not volatile memory unless you back up your personal computer every day to non volatile memory as when your hard drives go you lose something and ram when it fails there is no recovering the data no mater how important.

 

[Woomack]

don't know where to leave it so here it is:

quad channel @4100 18-20-20 1.35V and seems stable ( was working whole night )
AIDA64 is showing 4000 at anything above 4000, regardless how high is bclk.



4200 is sometimes losing 1-2 channels and I'm not sure how to make it run without issues. Voltages and most other settings are not helping. 100:133 strap is not working on my board so 4000 or 4266 at 100:133 is not even checking hardware after restart.

 

[Byórðæįr]

don't know where to leave it so here it is:

quad channel @4100 18-20-20 1.35V and seems stable ( was working whole night )
AIDA64 is showing 4000 at anything above 4000, regardless how high is bclk.

4200 is sometimes losing 1-2 channels and I'm not sure how to make it run without issues. Voltages and most other settings are not helping. 100:133 strap is not working on my board so 4000 or 4266 at 100:133 is not even checking hardware after restart.

So basically you are likely cooking the memory to death. You asking the cpu to keep track of 20/33 pull divider while having a flush of chip at about eight cycles with roughly a two cycle lag between the cpu telling the memory to change the memory state while trying to pull the reads of that memory at a faster speed than it can verify if it has actually changed what is memory yet.

I think you asking too much of the memory. the chart is the cpu cycles verse the memory cycles and how long the tasks take to complete and wiping a bank means the chip is all zeros and one to zero and zero to one is writing to the memory while some of the other numbers say that you are reading them memory back to the cpu before you have finished writing to it. You generally want to only read memory that you know is in a determined state of zero or one not one that is indeterminate of writing the answer down. Likely why you are getting weird errors. honestly at that pull down I would be using ecc memory.

Basically that means every time it tries to read at when writing to that address it tries to both read and write to the same location and keeps trying until it can both write the info to it and then read from it. I would loosen up the timings.

 

[Woomack]

This platform is designed for that memory frequency ( officially up to 4400 on KL-X ). Issues are because of so high frequency in quad channel mode and used memory which can't run at more relaxed timings without errors ( on this platform at least ). At 4100 all run stable ( pc is up for last 3 days without any error ).

Other thing is that CPU runs with enabled EIST/Turbo and C states and goes up to x45 so I find your graph pointless. Not to mention that there were never issues on other platforms when CPU divider was lower than RAM.
ECC is not helping in locked memory channels because of instability.

Weird errors mentioned by me are related to the motherboard and working dividers. It happened in the past and on some platforms it was fixed by BIOS update. On some it was impossible ( like x29.33 on some DDR3 platforms ).

 

[Byórðæįr]

Does not matter what the max is the point is that your cpu is having trouble doing the math of of 1/23 of second to 2 seconds. Roughly. When you send code from the cpu and the cpu can physically only work off the clocks you set in the bios, you can over clock the cpu but the frame of reference is the default clock of 3.3 GHz. Your memory timing are exactly what you put. Every time you try to send code form on to the other and the speeds are different the memory has to wait until the speeds are the same externally while you are telling the memory internally that it can write to the memory and read from it between writes from the cpu. It is timing issue. it is like a car engine trying to slap a cam shaft when the nodules are not in place. I aint your support tech so have fun meleting your ram chips, I have made that mistake in the past plenty of times myself.

 

[Johan45]

But that CPU had HT which grabs another 30% of the cycles and on top of that it's 10 cores with 20 threads. I highly doubt it's having trouble keeping up

 

[mackerel]

Maybe I'm missing something in the argument, but isn't the short version simply that ram and CPU cores are not synced to each other?

 

[Johan45]

Maybe I'm missing something in the argument, but isn't the short version simply that ram and CPU cores are not synced to each other?

And that the CPU can't keep up with the ram speed so the ram will be "waiting" for the CPU

 

[Byórðæįr]

The cpu is faster. the interconnecters are the bottle neck the internal speed of the memory is faster than the data can move from the cpu to the ram.

basically information is created and then stored on the ram.

At that point in order for the cpu to actually know what is on the ram when it is sending the data to the ram the ram is both trying to read and write to a block of zeros.

Not sure I can make that any easier since people who understand how ram works can tell that from the timings he posted.

Best non technical way to explain it is a clutch and ecu. The ecu allows the gear pin to slide into an open space between the teeth of a gear because the ecu can figure out where those empty spaces are based on physics and temperatures and power curves.

The ram is being spun like a gear and when the cpu tries to write to the gear the info gets clipped off instead of written. The ram internal speed does not help get the information from the cpu to the memory the timings control the delays to account for the delays of the interconnects between the cpu and the system memory. Which is why it should have been obvious.

 

[Johan45]

So by interconnect do you mean the cache or the traces

 

[wingman99]

Ram writes to the memory controller first from core data calls. So the syncing part of of ram is with the memory controller including Mesh on skylake X. Mesh is the timing to the cores, it is a network with routers.

 

[Byórðæįr]

the biggest issue is usually you have a grid of zeros and ones, it is faster to write ones to zeros but to do so you have to flush the bank which is that huge 600 clocks number, so you need to know if the pointer is set to one or zero. once you know if it is one or zero if it what you want you you return true, if not you return false and write the opposite with ras to cas time. The lag is ariteure itself. The eletric runs at atmoic weight of metal's least alloy so the difference between iron and alimium is normally insignifanct but at fractions of seconds adds lag based on the cheaper the board is. so at the technical level you start getting into how the wave forms are created what a retifer form is how to match the form of the signal at 3 billion waves per second is supposed to match speed with a signal that has waves at 2 billion waves per second and how they have to loop around what interfere they create by having to speed up and down the waves while transforming the wave size by increasing and decreasing the ampers which people due thinking heat is the only side effect. The signial is created on the cpu then stepped down in speed amplitude and cyclic rate passed over metal that may change metals a dozen times and then passed to chip that has to write a zero or one based on how tall the top of the sine wave is from the middle while not actully being able to measure the middle of the wave by seeing the height to the through.

Science is fun. Basically you have a series of waves that are exactly the same you are squashing and streching and have to have them match the shape they started with while fitting in a different size container. that is why you see the 60:3 pull down even though 4 GHz and 2 GHz would be a 2:1 pull down. which would be really easy to do increase the current by doubling the amps or cut it in half by quartering the amps, and the signal would match. I am not going to tell someone to run their system out of spec but the likely best setup based on the images provided by them would be

28 x 140 = 3920 MHz

18
28 to 56 clocks
2T

24 x 140 3369 24 14

which would allow the cpu to be closer to sine wave the ram needs and still not go much faster than the base clock they are using. that said drivers had to be writen for the intel chips when people started to run the frontside that fast. It is an x chip so it should be able to be set that way.