Clockless Processors

[ninthebin]

I didnt know where else to put this but if some evil mod decides it shouldnt be here - kick it

I was thinking about the concept of the clockless processor as it really is a fascinating venture...here is the article I came across:

http://www.computerworld.com/hardwaretopics/hardware/story/0,10801,76931,00.html?OpenDocument&~f

I wont repeat too much on what it says but it gets at limitations of clock driven processing.

I was thinking this as having more an application for multi logic processors...ok I admit I dont know much about these, and I did try and think about how it would work once and my brain overheated and throttled - so if you can explain a bit of how this works please share.

But im thinking it helping it from the point that if each part of the processor can act "independantly" of a set clock rythm then this can come about easier, as one thought I couldnt figure get was how something that has to not only work from distinguishing voltages as say a 0,1,2,3 etc...but then having a tiny fraction of a second to do this before it has to do it again.

 

[NookieN]

As that article mentioned, the idea of asynchonous logic circuits has been around for a while. Unfortunately, there haven't been many good VLSI design techniques for doing it.

The principle is pretty simple: every circuit that computes some logical value has a way of telling other circuits when its output is ready. Of course, actually doing that isn't easy. On method is to have a circuit compute a logical value and its complement (i.e. inverse) simultaneously. When both values have changed, you know the data is ready. Of course if the the value would not have changed from clock to clock in a synchonous system, it won't change in an asynchonous on either.

To get around this problem, more complex asynchronous systems will use communication between both the input and output circuits. The input circuit requests data from the output, the output acknowledges, the output provides valid data, the input acknowledges. Obviously, there are lots of different ways to accomplish this, and not all of them will be faster or more power efficient than synchonous circuits.

The industry is moving in that direction however. I know that a few years ago Intel redesigned the PII to be completely asynchronous. It ran almost three times as fast and with half the power (but of course it was still a PII). Even the P4 has some asynchronous circuitry in it. In the near-term we'll will probably see mostly chips that use a mix of synchronous and async, as that is easier to design that purely async and provides much of the same benefits.

 

[Penguin4x4]

So is this like Mac's and there processor's? If so, then the only way to OC will be to soldering and desoldering resistors,

 

[NookieN]

Macs definitely have a clock (though there is probably some asynchronous elements in the G4). And even in heavily asynchronous chips there would probably still be some sort clock that could be overclocked.

But how do you overclock a chip with _no_ clock? Well, there will always be chips with marginal silicon; some chips on a wafer are always better than others. Since asynchronous circuits are still heavily dependent on finite state machines (a conceptual graph of all the possible states a circuit can be in), there could be some way of reprogramming a state machine to run a little faster. Like CAS latency on ram, maybe you would be able to set a "logicA-ready delay" to X-2 instead of X.

 

[ninthebin]

but this wouldnt be like setting your FSB or Multiplier right - you would have to set timings on ALOT of components - and what if they move to say having timings on individual gates within the processor - you could have to reset timings on thousands upon thousands of parts, granted it would even be possible on that scale

 

[Intrepid]

What if there were no set timings at all. Timings are a form of clock to regulate the flow of info. Like having each individual car in a city have its own traffic light attached to it. That is kind of how I understand a computer to work, every piece of into has a traffic light on it for how far it will move in the next cycle. Now suppose each piece of info moved as soon as it could. Like in a city with no traffic lights. Things would move faster, but you wound need to completely re design the whole system in order to avoid accidents. But the way I would invasion a clockles computer is one in which the data or signal moves to the next point as soon as that point is free, the only limitation would be the maximum speed of the electricity through the wires. Though the implications THAT could have on cooling I guess would be kind of insane.

 

[Blueacid]

Cooling would be fun to run - when the CPU was running flat-out (in this instance, every single transistor would be working non-stop) then heat output would be a nightmare.

On the other hand, when idle, the temps would plummet - since the clock signal would be absent - hence less heat.


Surely these huge temperature fluctuations would perhaps shorten the life of the chips - due to expansion and contractions as the chips' usage changes?


Enlighten me please

 

[Intrepid]

Surely these huge temperature fluctuations would perhaps shorten the life of the chips - due to expansion and contractions as the chips' usage changes?

This is just what I was thinking. And it is exactly what hapens to a lot of A: water cooled systems and B: when you shut down any PC and then start it up again without giving it time to cool off evenly. I have heared stories of pins faling off of AMD XP chups, only once but I did hear it on AOA's boards, maybe here too. Cooling might have to use a special chip that can somehow predict the drmands of the CPU and modify the cooling mechanisim (whatever the cooling method be) to respond with more or less force. Cooling in such situation would have to be fast and able to switch from hot to cold really fast too, a pelt seems to be able to do this the fastest, but we need the cooler to e able to adjust very rapidly, say more than once a second.

 

[NookieN]

Clockless processors would actually run cooler and use less power than clocked processors. It's not that the transistors are always active in a clockless design, but rather they are _only_ active when there is a state change.

CMOS transistors in general only dissipate large amounts of power when they switch. In a clocked design, a lot of transistors are forced to switch with every clock cycle. For example, even if there is no change in data and nothing to process, every transistor in the cache must switch with each clock tick in order to save current data. In a clockless design, these transistors would just sit there, holding their current state, until their inputs changed.

 

[Intrepid]

So if this technology hit the desktop market in a few years we might see a move back to nice quiet passive cooling. That alone is a nice idea. though it would be the death of overclocking, though moding is still there. and perhaps there may be some other diferent way to increase or decrease the speed of these hypothetical chips.

 

[Since87]

though it would be the death of overclocking,

The death of "overclocking" maybe, but probably not the death of overvolting and serious cooling.

If you've got a bunch of independent modules waiting on inputs from other modules before they can proceed, then higher voltages and cooler temperatures should still speed everything up, and allow processing to occur faster. (All modules spend less time waiting for new input, and process their inputs faster.)

I'm fairly skeptical that we'll see a truly clockless processor anytime soon. I do digital logic design. (Xilinx FPGA's) The design complexity of a big clockless design, would require the software tools, used to design such chips, to get vastly "smarter" than they are now.

 

[Intrepid]

ugh I'd hate to design one. and I did say some other method would be used to speed them up. I do know that low temperatures will speed it up, like those superconductor thingys in the south pole, or around there. they are soo cold and move tons of energy very fast. I nkow IBM or somebody has looked into this for csome chips they are experimenting with, maybe it was Intel or Sun.

 

[Severian]

Asynchronous Processors

That article was simply about an asynchronous processor, as opposed to a truely clockless one. CPUs such as the Pentium 4 have ddr units (the execution unit in the P4's case), but no truely asynchronous processor has ever been made.

As far as future plans, there is only one I know of: The UltraSparc VII, which is out in about 2006-7, in which every unit will presumably be running at a different speed. IBM is going for multi-core "Cells", Intel for EPIC computing, while Sun is looking to asynchronous design for the future.

As far as a totally clockless processor goes, I don't think that concept is even remotely plausible. The way electronics works, it would quite literally be impossible to build a processor as we know them. Even a calculator would be impossible. The one other thing of intrest is analogue computing, which is said to be far more effective in certain areas. Unfortunately, thats all I know on that subject

 

[Cathar]

CPU makers could not release truly "un-clocked" CPU's as they would then have to way to speed-grade them.

I think a far more likely scenario is that the logic circuitry will be async, but the L1/L2 caches will still be clocked. This then allows speed grading of the CPU's, since the CPU logic can only run as fast as it is supplied with data. Also long-trace async memory technology is going to be next to impossible to do with today's parallel memory busses. So the memory and the caches will pretty much always need to be clocked.

So my guess is that while the internal logic of the CPU will be clock-less, there will still be a multiplier/FSB speed for a CPU which determines the effective L1/L2 cache speeds, and hence cache->core logic bandwidth, which in turn effectively places a measurable speed structure onto the back-end async-logic.

 

[ninthebin]

CPU makers could not release truly "un-clocked" CPU's as they would then have to way to speed-grade them.

graphics cards arent named from the speed of there GPUs they are given a nice little model number which increase to bare relevance to speedgrading...as you know the Ti4600 is better than the 4200 and the 5800 is better than the 4600...

I don't think that concept is even remotely plausible.

can you explain why not a little more - im a bit slow

 

[Cathar]

Sorry, I thought we were talking about CPU's here, not graphics cards...

 

[ninthebin]

I was simply giving an example of a naming scheme - it doesnt have to be named to the exact clock - a CPU example AMDs use a PR scheme, alright - its based around a clock scheme...but what im getting at is if Intel wanted to it could of called its 2GHz a Mega400series or something...the 2.2GHz could of then been the Mega450series or something, naming scheme complete

 

[Severian]

can you explain why not a little more - im a bit slow

Ok, well, the basics of Async processors.
While it is possible to have different speeds, the amount that is fed into it has to be adjusted corrispondingly. So for a factory metaphor, if part "A" of the production line can do a piece of the construction of half the time it takes part "B" of the production line to produce a part, they can both be made to run at full power by having two part "B"s, so that although "B" is still working at half the speed, it still feeds enough to "A" so that it is kept busy.

As for why a completely clockless processor wouldn't work, I'll first say what defines the speed of a processor now adays (also relevant to Async processors). A CPU can only run as fast as it's slowest part, usually the cache or pipeline. This is simply because it's the longest chain of transistors before a clock-gate. Transistors all have a switching time, so having 10 in a row would take roughly (ignoring wire length speed, which is a consideration, but makes things a bit complicated) 10 times the time to complete. The clock exists so that pieces of different lengths can still work together, otherwise the electrical bits would just get jumbled up. A clockless processor would have have no way or organising the bits, it would effectively be useful only for heating my coffee. To draw an analogy, say there were two parts of a processor working on a job, and the results those two parts had to be joined together (this is theoretically speaking). With a clock, they can both do them, wait until the next clock happens, and then join them. Without a clock, if one part worked faster, it would send it through, and would never have a hope of ever arriving at the right time to meet the other result it was meant to join up with.

Sorry if thats semi-illegible, but it's an attempt

 

[NookieN]

... A CPU can only run as fast as it's slowest part, usually the cache or pipeline. This is simply because it's the longest chain of transistors before a clock-gate. Transistors all have a switching time, so having 10 in a row would take roughly (ignoring wire length speed, which is a consideration, but makes things a bit complicated) 10 times the time to complete. The clock exists so that pieces of different lengths can still work together, otherwise the electrical bits would just get jumbled up.

Actually, I would say the slowest part of the processor is the clock itself. The clock does exist to make sure that all parts of the chip play nicely. But the whole advantage of an asynchronous design is that a single unit is not limited by the speed of the clock.

Let's start with the cache. Cache is slow because of the number of table-lookups and array access delays you have to wait on. With an async design, each of those lookups and access delays can be completed in their respective minimum times. Of course, current cache designs must be synchronous because of the way they store data. If you took away the clock, you would have millions of cross-coupled NOT gates sucking up power. But async designs are possible, abeit quite complicated.

As for the pipeline, I'm not sure what you mean. There's no such thing as "the pipeline" in a cpu. Basically the entire execution part of the chip is a pipeline. A pipeline consists of an execution stage followed by a register followed by and execution stage, etc. So without a clock, you're not limited by the longest execution stage. Each stage completes at its own rate.

An asynchronous processor isn't as simple as taking the clock out of a sync one and turning it on. It requires a complete redesign. The signals do not get jumbled in an async system because each circuit path is designed to know when it has valid data and when it does not. The units are all self-synchronizing through continuous bi-directional communication.

 

[Severian]

There is a thing called simplification, which is to be aimed for. Unfortunately, there's also often over-simplification, for which I may apologise

Actually, I would say the slowest part of the processor is the clock itself. The clock does exist to make sure that all parts of the chip play nicely. But the whole advantage of an asynchronous design is that a single unit is not limited by the speed of the clock.

Clock speeds are tailored to the CPU. Technically you could have a 10 GHz clock, which would be technically no more difficult to make, so long as it didn't need to actually govern over anything. So here I'm not quite sure what you mean. Transporting the clock signal does use a tremedous amount of power though, which is one of the drawbacks of a standard sync design.

Let's start with the cache. Cache is slow because of the number of table-lookups and array access delays you have to wait on. With an async design, each of those lookups and access delays can be completed in their respective minimum times. Of course, current cache designs must be synchronous because of the way they store data. If you took away the clock, you would have millions of cross-coupled NOT gates sucking up power. But async designs are possible, abeit quite complicated.

I am aware of that, as I said at one point, gates are by no means all of the picture, but it's a piece of simplification As far as a totally async desgin goes...well, I'll get to that later.

An asynchronous processor isn't as simple as taking the clock out of a sync one and turning it on. It requires a complete redesign. The signals do not get jumbled in an async system because each circuit path is designed to know when it has valid data and when it does not. The units are all self-synchronizing through continuous bi-directional communication.

Yes, but what I refer to was what would happen if you took the clock out of a normal processor (well, more or less)

But to the discrepancy: From everything that I've read, an async processor, or at least the one that Sun is working on for their UltraSparcVII, is not truely clockless, but instead has many different parts running at different clock rates with their own independant clocks. Hence "asynchronous". Not clockless, but not all synchronised together. You seem to infer that in your idea of an async chip, there is no chip, but the electrical paths are simply engineered to try and work so that it ends up working in unison. From what I had gathered, there were numerous units, each working at their own pace (and to a clock), all of which lead through another type of data gate (although I've forgotten the technical name this was given), which lets the bit pass when there is an appropriate space for it - making the parts which are not working in unison become cooperative nonetheless.

Anyway, that's my 2p for what it's worth.