- Joined
- Mar 7, 2008

I wrote this on another forum, but thought it might be interesting here too.

Below are my vague estimates of GPU die costs based on questionable data and assumptions. I'm really selling this aren't I?

Ada

AD102 $378

AD103 $179

AD104 $122

AD106 $70

Ampere

GA102 $114

GA103 $79

GA104 $53

GA106 $31

RDNA3

NAVI31 + 6x MCD $166

NAVI33 $41

RDNA2

NAVI21 $158

NAVI22 $79

NAVI23 $49

NAVI24 $19

Arc

DG2-512 $100

DG2-128 $29

How did I get these numbers?

I found the cost of a wafer in a general web search. Many of the sources I've never heard of before and I have no way to verify the sources of those numbers. The only ones I'd have some mild confidence in are the TSMC 7/5/3 ones as they are more frequently discussed, but it could also be everyone copying everyone else. I've assumed N6 is same as N7, and N4 is same as N5. Note however nvidia don't use N4, but 4N. I had wondered if I made a typo when I saw that but apparently it is a custom variation of the process for nvidia.

Right, so that's wafer cost taken as far as I can. Next, how many dies can we get from each? This is a function of two main variables: die area and defect rate. TSMC have openly stated a defect rate for N7 of below 0.1/cm2, and N5 was tracking similarly. I have found zero information about Samsung defect rate. Pick a number, any number! I decided to keep it at 0.1 for everything to keep calculation simple. With this we can get a number of expected "good" dies per wafer. Good in this sense means zero defects. In practice, some defect dies may still be usable if the bad part is mapped out. I thought I could estimate this by looking at how much effective area is reduced from cut-down products but this is going to be very time consuming so I'm not doing it at this point. The other unknown is binning. Just because a die is free from defects doesn't mean it'll necessarily meet the performance specification, so there may be some loss from that path. Again, it may be used in lower tier bin to recycle it. Given the complexity I've not taken either of these into consideration. I assumed a good die is defect free and will meet performance specifications.

If you're wondering how much of an impact defect rate makes in this, not a massive amount. Looking at NAVI21, going from 0.1 to 0.09 defect rate means we go from 59 to 62 expected good dies, reducing the cost from $158 to $150. If we pick a small die like NAVI24, we go from 498 to 503 expected good dies, $18.7 to $18.5.

Below are my vague estimates of GPU die costs based on questionable data and assumptions. I'm really selling this aren't I?

Ada

AD102 $378

AD103 $179

AD104 $122

AD106 $70

Ampere

GA102 $114

GA103 $79

GA104 $53

GA106 $31

RDNA3

NAVI31 + 6x MCD $166

NAVI33 $41

RDNA2

NAVI21 $158

NAVI22 $79

NAVI23 $49

NAVI24 $19

Arc

DG2-512 $100

DG2-128 $29

How did I get these numbers?

I found the cost of a wafer in a general web search. Many of the sources I've never heard of before and I have no way to verify the sources of those numbers. The only ones I'd have some mild confidence in are the TSMC 7/5/3 ones as they are more frequently discussed, but it could also be everyone copying everyone else. I've assumed N6 is same as N7, and N4 is same as N5. Note however nvidia don't use N4, but 4N. I had wondered if I made a typo when I saw that but apparently it is a custom variation of the process for nvidia.

Right, so that's wafer cost taken as far as I can. Next, how many dies can we get from each? This is a function of two main variables: die area and defect rate. TSMC have openly stated a defect rate for N7 of below 0.1/cm2, and N5 was tracking similarly. I have found zero information about Samsung defect rate. Pick a number, any number! I decided to keep it at 0.1 for everything to keep calculation simple. With this we can get a number of expected "good" dies per wafer. Good in this sense means zero defects. In practice, some defect dies may still be usable if the bad part is mapped out. I thought I could estimate this by looking at how much effective area is reduced from cut-down products but this is going to be very time consuming so I'm not doing it at this point. The other unknown is binning. Just because a die is free from defects doesn't mean it'll necessarily meet the performance specification, so there may be some loss from that path. Again, it may be used in lower tier bin to recycle it. Given the complexity I've not taken either of these into consideration. I assumed a good die is defect free and will meet performance specifications.

If you're wondering how much of an impact defect rate makes in this, not a massive amount. Looking at NAVI21, going from 0.1 to 0.09 defect rate means we go from 59 to 62 expected good dies, reducing the cost from $158 to $150. If we pick a small die like NAVI24, we go from 498 to 503 expected good dies, $18.7 to $18.5.

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