It looks like they're basically doing the same thing on a memory bus as the current P4 front side bus. They transfer 4-bits per clock cycle as opposed to 1 in sdram or 2 in ddr-sdram (I could give technical details, but you can find those at the site above).
It sounds good, but I don't know if it will be as reliable as they say it will. According to their faq, the first chipsets that support it will be delivered by SiS and VIA -- and it wouldn't surprise me if it takes them a couple tries to get it right.
No dual channel is 4-bank memory. It's 128-bits wide, while single channel is 64, but runs at the same speed and thus is twice as fast.
QBM looks like it really does transfer 4 bits per clock along a 64 bit bus. I suppose they could have called it 'QDR'. But since the mechanism is a little different than DDR maybe they figured QBM is a better name.