OP
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I added some stuff about the wire trick (thanks for the idea and link JimmyK)...I also added some more stuff to the cooling area.
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The Newbie's Guide to Overclocking.
- Thread starter altec
- Start date
Gautam said:All looks absolutely great. Maybe add some stuff about fsb/dram ratios, and when people should use them, and perhaps a basic skimming on memory timings other than CAS latency. Since you've already covered so much, might as well take the rest down!
Added something about ras/cas timing and fsb:memory ratio into the summary.
OP
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I added some information on the wire trick to make voltage changes. Enjoy!
Thanks to hitechjb1 for the link, and edward2...for making the thread.
Good luck
Thanks to hitechjb1 for the link, and edward2...for making the thread.
Good luck
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altec said:
I am surprised nobody else has picked up on this (maybe somebody has but I havent read the subsequent posts!) But to get to the lower multipliers requires connecting NOT blowing the last L3 - obviously assuming that the 8x bit of the cpu is set for the higher multis in the first place.
OP
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Alright OC Detective....you know me, I always get this crap wrong. I asked if it was correct, and got a yes answer, but I will go change it. If you see anything else that isn't correct, please let me know.
What is cycle time and frequency
Nano-second (ns) is 1/1,000,000,000 of a second or 10^-9 of a second. It measures the cycle time of the clock for the memory chip, and other chips such as CPU, GPU, motherboard ...
Pico-second (ps) is 1/1,000,000,000,000 of a second or 10^-12 of a second.
The higher the clock, the faster the data transfer and computation can be carried out.
The corresponding frequency of a clock period of 1 ns is 1 GHz. (1GHz = 1,000,000,000 Hz = 1,000,000,000 cycle/sec)
frequency = 1 / cycle_time
The famous Tbred B 1700+ DLT3C can be overclocked to 2.5 GHz, or 2,500,000,000 Hz. Its cycle time is 400 ps or 0.4 ns.
For a DDR400 memory module with 5 ns DRAM chips, 5 ns is the cycle time of the clock of the memory chip. The corresponding clock frequency is 200 MHz.
A memory module consists of 8 memory chips on one side to form a 64 bits data-path (or 8 bytes data-path). Each memory chip contributes 8 I/O bits. Hence if the memory is running with a 200 Mhz clock, and data is transferred on both the rising edge and falling edge of the clock (DDR or double data rate), the max data rate the memory module can transfer is
max memory data rate (or bandwidth) = 200 x 2 x 8 = 3200 M byte/s (or called PC3200)
So for 5 ns chip, max bandwidth = 200 x 2 x 8 = 3200 MB/s (called PC3200)
So for 4.5 ns chip, max bandwidth = 222 x 2 x 8 = 3552 MB/s (called PC3500)
...
Nano-second (ns) is 1/1,000,000,000 of a second or 10^-9 of a second. It measures the cycle time of the clock for the memory chip, and other chips such as CPU, GPU, motherboard ...
Pico-second (ps) is 1/1,000,000,000,000 of a second or 10^-12 of a second.
The higher the clock, the faster the data transfer and computation can be carried out.
The corresponding frequency of a clock period of 1 ns is 1 GHz. (1GHz = 1,000,000,000 Hz = 1,000,000,000 cycle/sec)
frequency = 1 / cycle_time
The famous Tbred B 1700+ DLT3C can be overclocked to 2.5 GHz, or 2,500,000,000 Hz. Its cycle time is 400 ps or 0.4 ns.
For a DDR400 memory module with 5 ns DRAM chips, 5 ns is the cycle time of the clock of the memory chip. The corresponding clock frequency is 200 MHz.
A memory module consists of 8 memory chips on one side to form a 64 bits data-path (or 8 bytes data-path). Each memory chip contributes 8 I/O bits. Hence if the memory is running with a 200 Mhz clock, and data is transferred on both the rising edge and falling edge of the clock (DDR or double data rate), the max data rate the memory module can transfer is
max memory data rate (or bandwidth) = 200 x 2 x 8 = 3200 M byte/s (or called PC3200)
So for 5 ns chip, max bandwidth = 200 x 2 x 8 = 3200 MB/s (called PC3200)
So for 4.5 ns chip, max bandwidth = 222 x 2 x 8 = 3552 MB/s (called PC3500)
...
Last edited:
Frequency, clock, period of synchronous operations
CPU, memory, PCI bus, GPU, ... are driven by a clock which oscillates many cycles per second. Cycle per sec is also know as Hertz (Hz). E.g. the famous Tbred B 1700+ can be overclocked to around 2,500,000,000 cycles/sec (or 2.5 GHz), DDR400 memory can operate at a clock frequency of 200,000,000 cycles/sec (or 200 MHz). The electronic components that are driven by a clock perform certain operatioins (electrically and logically) at each clock tick, and move on to the next one, .... This is also called the synchronous mode of operation.
The reciprocal of frequency f is called the period T of the clock. T=1/f. So the period T is the time spacing between two operations of the electronic componet, e.g CPU, memory, GPU, ... E.g for a 2.5 GHz CPU, the time spacing between each clock tick is 1/2.5GHz = 0.4 ns or 400 ps. The time spacing between each clock tick in a DDR400 memory module is 1/200MHz = 5 ns.
Latency
Latency is a measure of time to complete certain operations. For synchronous mode such as CPU, memory, ..., each operation is measured in terms of number of cycles. An operation can be a large operation such as the Read or Write operation, or the smaller internal operation of a Read or Write operation.
For DRAM memory modules that are driven by a clock is called synchronous DRAM (SDRAM). With this in mind, the memory operations can be described in terms of number of cycles instead of time. When we move from DDR400 to DDR500, or a CPU from 2GHz to 3GHz, each operation takes propotionally shorter time due to faster silicon process, but the number of cycles to achieve an operation remain the same, and the interrelationship between operations in terms of cycles remains the same, unless there is a change in architechture and timing, ...
DRAM is organized in rows and columns of storage bits. The intersection of a row and a column is a bit of data. To access data, address is decoded into row and column addresses. First, the row corresponding to the decoded row address is accessed followed by sensing of all the bits in that row (and are stored in the sense amplifier during the Read operation), and then the corresponding columns are accessed and data output. In many case, multiple columns are accessed and output as a sequence of data that are located on the same row to save row access overhead, this is called the burst mode of operation commonly used for large block/page of data (this is where CAS latency comes in).
Here use Read operation to illustrate the concept. After memory controller issues Read command and address, a DRAM read operation is like this:
1. DRAM module decodes address into row address and column address
2. Activates word-line (row address) and detect and store all the row data by the sense amplifiers
3a. Activates column (column address) and outputs data
3b. In case of multiple column access (as discuss earlier), a sequence of column data is output.
4. Restore data back to the DRAM cells and precharge for next operation.
The tRCD latency - is the time or number of cycles to perform step 2. Typically, tRCD takes 2 or 3 cyles to complete.
The CAS latency - is the time or number of cycles to perform step 3a. In case of step 3b (in case multiple N column data are output), the total latency = N x CAS. Typically, CAS latency takes 2 to 3 cycles to complete.
The tRP latency - is the time or number of cycles to perform step 4. Typically, tRP takes 2 or 3 cycles to complete.
So the latency of a DRAM Read operation is tRCD + N x CAS + tRP, where typically N = 1 or 4 or 8 (or even more), depends on the number of column access per memory access. This is the total number of cycles for a Read operation.
Remember tRCD = 2 or 3, CAS = 2 (try to avoid setting to CAS 3), tRP = 2 or 3,
For 1 column access, the total latency of Read operation = tRCD + CAS + tRP
For 4 column access, the total latency of Read operation = tRCD + 4 CAS + tRP
For 8 column access, the total latency of Read operation = tRCD + 8 CAS + tRP
etc, etc.
Time for first data output from address decode = tRCD + CAS
Time for data output in multiple column access,
Time for second data output = tRCD + 2 x CAS
Time for third data output = tRCD + 3 x CAS
etc, etc.
Latency is different than memory bandwidth. Memory bandwidth is solely determined by the memory bus frequency and FSB frequency, and NOT latency. It is how fast the memory clock or FSB clock can run, regardless of whether the memory module has shorter or longer latency.
E.g. all DDR400 memory module can run at same memory speed 200MHz, regardles of their latency, to deliver a maximum bandwidth given by 2x8x200 = 3200 MB/s. x2 because of DDR meaning data are transferred at both the rising and falling edges of the clock. x8 because there are 8 bytes in the memory bus. But some low latency module can finish each of the above steps tRCD or CAS or tRP in smaller number of cycles, e.g. at 2-2-2. Most module can finish each of these steps in longer number of cycles, e.g. 3-3-2.
CAS latency is the most important since it is the time to output 1 bit (single column access) or many bit of data (multiple column access) (as described earlier). For all today's memory module, always set CAS to 2, and I find that almost all modules in the market now can be able to do that.
Set tRCD and tRP to 2 is possible. If not, set them to 3 is OK, not much penalty.
PS:
RAS to CAS delay is tRCD, the time to perform step 2 described in the prevous post. Typically it is 2 or 3. 2 is better.
RAS precharge, or RAS precharge delay is tRP, the time to preform step 3 described earlier. Typically it is 2 or 3. 2 is better.
tRAS, active to precharge delay, is the minimum time for an active access (to perform a single row and column access. So tRAS >= tRCD + CAS. It is the least important number on performance, set it to 5 or 6 is OK. (Be honest, I am sometime confused by how the bios is implementing it, and the definiton is not very clear. But luckily, it is not of big significant.) For example, typically, tRCD = 3, CAS =2 , so tRAS >= 5 (6 is OK, 5 should work). If tRCD = 2, CAS = 2, so tRAS >= 4 (5, 6 is OK).
Sometimes bios setting, and how the bios takes the number and operates become even harder to understand, since it is mb specific and also depends how the programs read those data and present them.
After going through all these terms, operation details, theory, ... just to use and set up memory is VERY SIMPLE. For current mb's and memory modules, 6-3-3-2 is almost certain would work, and it won't lose too much performance to more aggressive timing 5-2-2-2, 2-3% at most. Those number are in this order: tRAS-tRCD-tRP-CAS.
But setting FSB as high as possible, as permitted by mb and memory, even having to go from 5-2-2-2 to 6-3-3-2, would benefit the most for overall system bandwidth, 3D video and gaming performance. Set CAS to 2 is the most important among these magic numbers, and I find almost all module on the market today can do CAS2.
CPU, memory, PCI bus, GPU, ... are driven by a clock which oscillates many cycles per second. Cycle per sec is also know as Hertz (Hz). E.g. the famous Tbred B 1700+ can be overclocked to around 2,500,000,000 cycles/sec (or 2.5 GHz), DDR400 memory can operate at a clock frequency of 200,000,000 cycles/sec (or 200 MHz). The electronic components that are driven by a clock perform certain operatioins (electrically and logically) at each clock tick, and move on to the next one, .... This is also called the synchronous mode of operation.
The reciprocal of frequency f is called the period T of the clock. T=1/f. So the period T is the time spacing between two operations of the electronic componet, e.g CPU, memory, GPU, ... E.g for a 2.5 GHz CPU, the time spacing between each clock tick is 1/2.5GHz = 0.4 ns or 400 ps. The time spacing between each clock tick in a DDR400 memory module is 1/200MHz = 5 ns.
Latency
Latency is a measure of time to complete certain operations. For synchronous mode such as CPU, memory, ..., each operation is measured in terms of number of cycles. An operation can be a large operation such as the Read or Write operation, or the smaller internal operation of a Read or Write operation.
For DRAM memory modules that are driven by a clock is called synchronous DRAM (SDRAM). With this in mind, the memory operations can be described in terms of number of cycles instead of time. When we move from DDR400 to DDR500, or a CPU from 2GHz to 3GHz, each operation takes propotionally shorter time due to faster silicon process, but the number of cycles to achieve an operation remain the same, and the interrelationship between operations in terms of cycles remains the same, unless there is a change in architechture and timing, ...
DRAM is organized in rows and columns of storage bits. The intersection of a row and a column is a bit of data. To access data, address is decoded into row and column addresses. First, the row corresponding to the decoded row address is accessed followed by sensing of all the bits in that row (and are stored in the sense amplifier during the Read operation), and then the corresponding columns are accessed and data output. In many case, multiple columns are accessed and output as a sequence of data that are located on the same row to save row access overhead, this is called the burst mode of operation commonly used for large block/page of data (this is where CAS latency comes in).
Here use Read operation to illustrate the concept. After memory controller issues Read command and address, a DRAM read operation is like this:
1. DRAM module decodes address into row address and column address
2. Activates word-line (row address) and detect and store all the row data by the sense amplifiers
3a. Activates column (column address) and outputs data
3b. In case of multiple column access (as discuss earlier), a sequence of column data is output.
4. Restore data back to the DRAM cells and precharge for next operation.
The tRCD latency - is the time or number of cycles to perform step 2. Typically, tRCD takes 2 or 3 cyles to complete.
The CAS latency - is the time or number of cycles to perform step 3a. In case of step 3b (in case multiple N column data are output), the total latency = N x CAS. Typically, CAS latency takes 2 to 3 cycles to complete.
The tRP latency - is the time or number of cycles to perform step 4. Typically, tRP takes 2 or 3 cycles to complete.
So the latency of a DRAM Read operation is tRCD + N x CAS + tRP, where typically N = 1 or 4 or 8 (or even more), depends on the number of column access per memory access. This is the total number of cycles for a Read operation.
Remember tRCD = 2 or 3, CAS = 2 (try to avoid setting to CAS 3), tRP = 2 or 3,
For 1 column access, the total latency of Read operation = tRCD + CAS + tRP
For 4 column access, the total latency of Read operation = tRCD + 4 CAS + tRP
For 8 column access, the total latency of Read operation = tRCD + 8 CAS + tRP
etc, etc.
Time for first data output from address decode = tRCD + CAS
Time for data output in multiple column access,
Time for second data output = tRCD + 2 x CAS
Time for third data output = tRCD + 3 x CAS
etc, etc.
Latency is different than memory bandwidth. Memory bandwidth is solely determined by the memory bus frequency and FSB frequency, and NOT latency. It is how fast the memory clock or FSB clock can run, regardless of whether the memory module has shorter or longer latency.
E.g. all DDR400 memory module can run at same memory speed 200MHz, regardles of their latency, to deliver a maximum bandwidth given by 2x8x200 = 3200 MB/s. x2 because of DDR meaning data are transferred at both the rising and falling edges of the clock. x8 because there are 8 bytes in the memory bus. But some low latency module can finish each of the above steps tRCD or CAS or tRP in smaller number of cycles, e.g. at 2-2-2. Most module can finish each of these steps in longer number of cycles, e.g. 3-3-2.
CAS latency is the most important since it is the time to output 1 bit (single column access) or many bit of data (multiple column access) (as described earlier). For all today's memory module, always set CAS to 2, and I find that almost all modules in the market now can be able to do that.
Set tRCD and tRP to 2 is possible. If not, set them to 3 is OK, not much penalty.
PS:
RAS to CAS delay is tRCD, the time to perform step 2 described in the prevous post. Typically it is 2 or 3. 2 is better.
RAS precharge, or RAS precharge delay is tRP, the time to preform step 3 described earlier. Typically it is 2 or 3. 2 is better.
tRAS, active to precharge delay, is the minimum time for an active access (to perform a single row and column access. So tRAS >= tRCD + CAS. It is the least important number on performance, set it to 5 or 6 is OK. (Be honest, I am sometime confused by how the bios is implementing it, and the definiton is not very clear. But luckily, it is not of big significant.) For example, typically, tRCD = 3, CAS =2 , so tRAS >= 5 (6 is OK, 5 should work). If tRCD = 2, CAS = 2, so tRAS >= 4 (5, 6 is OK).
Sometimes bios setting, and how the bios takes the number and operates become even harder to understand, since it is mb specific and also depends how the programs read those data and present them.
After going through all these terms, operation details, theory, ... just to use and set up memory is VERY SIMPLE. For current mb's and memory modules, 6-3-3-2 is almost certain would work, and it won't lose too much performance to more aggressive timing 5-2-2-2, 2-3% at most. Those number are in this order: tRAS-tRCD-tRP-CAS.
But setting FSB as high as possible, as permitted by mb and memory, even having to go from 5-2-2-2 to 6-3-3-2, would benefit the most for overall system bandwidth, 3D video and gaming performance. Set CAS to 2 is the most important among these magic numbers, and I find almost all module on the market today can do CAS2.
Analogy on Bus Speed, Bandwidth and Latency:
In a two lane highway, all vehicles in BOTH lanes are moving at 60 mph. All the vehicles on one lane (called CAS3) are all identical long vans. All the vehicles on the other lane (called CAS2) are all identical compact cars.
Since vehicles in both lanes are driving at SAME speed, the total vehicle-length passed at a given point per second in both lanes are the same. This is analogous to the memory bus speed or bandwidth being the SAME in two different memory buses each connected to a different module, one to CAS3 and one to CAS2. Clock pulses are moving in both buses at same rate, even one memory has higher latency CAS3 (takes more time to finish an operation) than the other CAS2.
But if you count the number of vehicles passing through each lane per second, the number on lane CAS3 is much smaller than that on lane CAS2. This is analogous to the number of data packets that can be delivered to the CPU per second on the bus by CAS3 memory is much less than that by CAS2 memory.
Data (clock pulses) are moving at the same speed in both cases (same memory frequency, same BW), but the data packets received by the CPU is much less in the case of larger latency memory (CAS3) than that of smaller latency memory (CAS2)
In a two lane highway, all vehicles in BOTH lanes are moving at 60 mph. All the vehicles on one lane (called CAS3) are all identical long vans. All the vehicles on the other lane (called CAS2) are all identical compact cars.
Since vehicles in both lanes are driving at SAME speed, the total vehicle-length passed at a given point per second in both lanes are the same. This is analogous to the memory bus speed or bandwidth being the SAME in two different memory buses each connected to a different module, one to CAS3 and one to CAS2. Clock pulses are moving in both buses at same rate, even one memory has higher latency CAS3 (takes more time to finish an operation) than the other CAS2.
But if you count the number of vehicles passing through each lane per second, the number on lane CAS3 is much smaller than that on lane CAS2. This is analogous to the number of data packets that can be delivered to the CPU per second on the bus by CAS3 memory is much less than that by CAS2 memory.
Data (clock pulses) are moving at the same speed in both cases (same memory frequency, same BW), but the data packets received by the CPU is much less in the case of larger latency memory (CAS3) than that of smaller latency memory (CAS2)
Analogy for FSB, CAS2, CAS3 latency and bandwidth for DRAM memory
An analogy is that, when you watch TV live of Q&A between one questioner and two responders. The questioner is located from one part of the world, and the two responders are located from the opposite part of the world. The two responders, one (called CAS2) speaks faster than the other (called CAS3). You see the delay between the question and the first word of the answer (from one of the responder), this is first access latency (tRCD). But once the answer is started (assuming no interrupt), between the faster speaker (CAS2) and the slower speaker (CAS3), you don't feel the difference since both voices are streaming back with same bandwidth from satellite (same FSB bandwidth). Both the faster responder and the slower responder can speak the answer smoothly, due to same satellite bandwidth (FSB bandwidth). For the same answer (same number of words), the faster responder will finish the answer faster than the slower responder (because CAS2 has lower latency than CAS3, and so finishes earlier than CAS3).
So if the answer has N words, and for simplicity, each word is spoken with equal length of time CAS2 and CAS3 respectively by the two responders (CAS3 > CAS2), then
the time to complete answer by responder CAS2 = tRCD + N x CAS2
the time to complete answer by responder CAS3 = tRCD + N x CAS3
An analogy is that, when you watch TV live of Q&A between one questioner and two responders. The questioner is located from one part of the world, and the two responders are located from the opposite part of the world. The two responders, one (called CAS2) speaks faster than the other (called CAS3). You see the delay between the question and the first word of the answer (from one of the responder), this is first access latency (tRCD). But once the answer is started (assuming no interrupt), between the faster speaker (CAS2) and the slower speaker (CAS3), you don't feel the difference since both voices are streaming back with same bandwidth from satellite (same FSB bandwidth). Both the faster responder and the slower responder can speak the answer smoothly, due to same satellite bandwidth (FSB bandwidth). For the same answer (same number of words), the faster responder will finish the answer faster than the slower responder (because CAS2 has lower latency than CAS3, and so finishes earlier than CAS3).
So if the answer has N words, and for simplicity, each word is spoken with equal length of time CAS2 and CAS3 respectively by the two responders (CAS3 > CAS2), then
the time to complete answer by responder CAS2 = tRCD + N x CAS2
the time to complete answer by responder CAS3 = tRCD + N x CAS3
I added four more related to some basics for frequency, bandwidth, latency, ... related to FSB, and memory. They are originally from the memory section. If you think it is better just to link there instead of copy, pls just let me know and I can change.
OP
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Bumpity bump bump
Any other ideas to put in here?
Any other ideas to put in here?
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STICKY!!!!!!!
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maybe i should read it first. but we need a o/cing guide, might as well sticky it.
OP
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Read it modena, and tell me if anything is wrong, confusing, misleading, etc...
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ok ive read up to the cooling part. you might want to add the the tt smt fn 2 actually goes up to 6000rpm and will move close to 90cfm and at more static pressure than the vantec tornado. and add that the static pressure is really good for ramming air through those thin fin heatsinnks.
also you might want to add that ducting lowers temps greatly. im planning on making a ducting guide with pics for Gcooling this week. when im done ill send you the link and you could put it in there if you wanted to.
also you might want to add that ducting lowers temps greatly. im planning on making a ducting guide with pics for Gcooling this week. when im done ill send you the link and you could put it in there if you wanted to.
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HERE IS A LINK WWITH MORE INFO ON THE SMT FAN @
*********!!!!!!! THE AUTO SHIFT KEY IS SCREWING EVERYTHING UP!!!!!
*********!!!!!!! THE AUTO SHIFT KEY IS SCREWING EVERYTHING UP!!!!!
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