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New Socket Late 2008

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holy, snapping arsels 16-24M L2 cache, I remember the first 18 inch square 1Meg ram BOARD. Do you think the larger socket will allow for a larger die as the reason for getting that much cache?
 
Cache doesn't deal with pin count thats another thing all togeather more like for the other added on board items they will be putting on or the interconnects between that and the mobo.

They could drop a 100Meg cache on the CPU today but it just costs so much since its consumes alot of space on the die itself, let alone to power it as well. Its a cost issue not a pin connection issue.
 
AlabamaCajun said:
holy, snapping arsels 16-24M L2 cache, I remember the first 18 inch square 1Meg ram BOARD. Do you think the larger socket will allow for a larger die as the reason for getting that much cache?
yea it also prolly the other reason intel is going to a larger socket.
 
deathman20 said:
Cache doesn't deal with pin count thats another thing all togeather more like for the other added on board items they will be putting on or the interconnects between that and the mobo.

They could drop a 100Meg cache on the CPU today but it just costs so much since its consumes alot of space on the die itself, let alone to power it as well. Its a cost issue not a pin connection issue.
Sorry, you missed my point. Going to a larger chip carrier with more pins allows for larger dies!
 
AlabamaCajun said:
Sorry, you missed my point. Going to a larger chip carrier with more pins allows for larger dies!
Well, we dunno yet about die size. The tech is being shrunk 20nm, and I honestly doubt that even 2 dual-core 45nm's would be bigger than the amount of space the 2 dies in a Kentsfield take up. My guess is that the Quad core die will be smaller than the current Conroe die, which will mean the chip itself will be the same size as the current LGA775's, meaning smaller pins, or if the die is A LOT smaller they might shrink the chip too, which means REALLY small pins ^^. We'll just have to wait and see.

-Mobious-
 
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