I have done quite a bit of testing on DC and SC using a NF7-S rev 2.0 and 1700+, CPU Interface enable/disable, I have some detailed number. Instead of listing all these numbers, let me summarize:
Testing done w/ 512 MB x 2 timing 6-3-3-2 at 2.9 V
Vdd chipset at 1.7 V
With CPU Interface disable:
- DC memory bw efficiency = 88-89%
- SC memory bw efficiency = 87-88%
(1-2% lower for SC, this agrees with the number 1-3% I have been using for SC/DC difference at same FSB)
At very lower CPU speed,
1800 MHz, bw efficiency dropped 1%
1600 MHz, bw efficiency dropped 3%
1500 MHz, bw efficiency dropped 8%
With CPU Interface enable:
- DC memory bw efficiency = 94-96%
- SC memory bw effiiency = 91-94 %
(2-3% lower for SC, this agrees with the number 1-3% I have been using for SC/DC difference at same FSB)
At very lower CPU speed,
1800 MHz, bw efficiency dropped 5% <-- fast decode, slow CPU took the toll, went down faster ??
1600 MHz, bw efficiency dropped 5% <-- fast decode, slow CPU took the toll, went down faster ??
1500 MHz, bw efficiency dropped 8%
From these numbers, DC and SC track each other closely at the same FSB by 1-3% efficiency difference (SC lower). So DC and SC are not the issue, we know how they behave and tradeoff. DC with 2-3% higher efficiency and SC with few MHz higher in FSB overclocking. The end result in nforce2 between the two is within 1-2% (can be either way if higher FSB for SC is allowed).
Important thing is that the CPU Interface (fast decode) bw efficiency in the mid 90% for high CPU speed. And the right combination of the correct bios and FSB_sense mod would enable to run FSB stable (e.g. prime95) around 230 MHz. The 6-7% in bw efficiency is equivalent to 15 MHz FSB w/ CPU Interface disabled.
With CPU Interface enable,
For older rev 2.0 board, bios 14 would run at ~230 MHz, memory bw efficiency 95%
For older rev 2.0 board, bios 10 would run at ???, memory bw efficiency ?? <-- need some data
For older rev 2.0 board, FSB_Sense mod would run at ??, memory bw efficiency ?? <-- need some data
For newer rev 2.0 board, bios 10 + FSB_Sense 166 mod would run at ~230 MHz, memory bw efficiency ~95 %
For newer rev 2.0 board, bios 14 + FSB_Sense 166 mod would run at ?? MHz, memory bw efficiency ?? <-- need some data
I tested 3Dmark01/03, it could run as high as 238 MHz stable, but prime95 failed at that speed. Also could boot windows at 245 MHz with very unstable Sandra memory bandwidth benchmark. Some vdd mod to 1.85V and memory timing to 7-3-3-2.5 or 7-3-3-3 for FSB above 235-240 MHz.
I suspect due to memory controller, and CPU decode limitation at such FSB speed with CPU Interface enable, currently seems to be max at around 230-235 MHz FSB or 36xx MB/s integer bandwidth (whichever is smaller), without extreme chipset Vdd mod and cooling.
Still why boards (older and newer, if there is really such distinction) behave differently w/ bios version, and FSB_sense setting, ...
I can already cross 230mhz at CL2.5, btw. 232 seems to be the max, but I haven't tried much higher than 6-3-3-2.
