- Thread Starter
- #21
Hi again! 
I'll try to answer all of yr questions as well as I can.
First of all yr last remark about circuit droop, yes you are right, that's a typo.
The specsheets give the VID pin info. This is a voltage value that is used for the CPU to comunicate with the PWM controller chip. When you select a voltage in bios, the PWM controller implements this voltage, and sets the tension on a number of CPU pins. As far as I understand it, the proc looks at these voltages, and sends a pwgd signal, pulling one of the pwm controller pins to high, telling the pwm chip that it has accepted the voltage layout. If the pwm chip receives low voltage on this pin, it means power-no-good, and it switches the Vcore supply off.
The whole VID pin layout and the values, are not of any direct relation with the actual Vcore supplied accross the Vcc and Vss pins of the proc. I think you have to see the VID values as control values between cpu and pwm controller, nothing else. Their tolerance range lays outside that of the VRD loadline tolerance.
What I cannot oversee from here is how many Amps yr EE proc pulls under load, and this whole story is just about that (droop= loss of tension (V) due to resistance in the conductor at high current (A). These values, in our case, always lay outside of the design specs of pwm unit and cpu, since we OC the s**t out of them. So even if everything is designed to have droop under control at say 70A pwm output, when we get to +50 FSB, the whole picture is distorted, and we'r pulling in excess of 95 - 100 Amps.
This is why the best way to come to grips with the Vcore situation, (especially on socket 478 / Prescott > 3.0), is to get a proper testpoint, and observe what is actually going on.
The software measurements, have some inaccuracy, in the range of 0.02 - 0.04 V, just enough to make them useless.
Reality is that when you'r doing a high OC on thse CPU's, the window of good Vcore values, is smaller the higher you get. What I mean is that when at stock speeds, any Vcore between (Prescott) say 1.40V and 1.55V will allow the chip to run well and stable. Now, as FSB rises, this window narrows to a point where it has to lay between say for example (like my cpu at 255FSB) 1.527 and 1.519 Volts. Any value outside of this will cause instability. At 250 FSB the window is between 1.490 and 1.535 Volts.
To get you to see all this in perspective, I'd abandon all the Intel theories and specs, since we work outside of their spec anyways, and quite a bit so. Let's go by our own findings, they lead to higher OC's!!
I'll try to answer all of yr questions as well as I can. First of all yr last remark about circuit droop, yes you are right, that's a typo.
The specsheets give the VID pin info. This is a voltage value that is used for the CPU to comunicate with the PWM controller chip. When you select a voltage in bios, the PWM controller implements this voltage, and sets the tension on a number of CPU pins. As far as I understand it, the proc looks at these voltages, and sends a pwgd signal, pulling one of the pwm controller pins to high, telling the pwm chip that it has accepted the voltage layout. If the pwm chip receives low voltage on this pin, it means power-no-good, and it switches the Vcore supply off.
The whole VID pin layout and the values, are not of any direct relation with the actual Vcore supplied accross the Vcc and Vss pins of the proc. I think you have to see the VID values as control values between cpu and pwm controller, nothing else. Their tolerance range lays outside that of the VRD loadline tolerance.
What I cannot oversee from here is how many Amps yr EE proc pulls under load, and this whole story is just about that (droop= loss of tension (V) due to resistance in the conductor at high current (A). These values, in our case, always lay outside of the design specs of pwm unit and cpu, since we OC the s**t out of them. So even if everything is designed to have droop under control at say 70A pwm output, when we get to +50 FSB, the whole picture is distorted, and we'r pulling in excess of 95 - 100 Amps.
This is why the best way to come to grips with the Vcore situation, (especially on socket 478 / Prescott > 3.0), is to get a proper testpoint, and observe what is actually going on.
The software measurements, have some inaccuracy, in the range of 0.02 - 0.04 V, just enough to make them useless.
Reality is that when you'r doing a high OC on thse CPU's, the window of good Vcore values, is smaller the higher you get. What I mean is that when at stock speeds, any Vcore between (Prescott) say 1.40V and 1.55V will allow the chip to run well and stable. Now, as FSB rises, this window narrows to a point where it has to lay between say for example (like my cpu at 255FSB) 1.527 and 1.519 Volts. Any value outside of this will cause instability. At 250 FSB the window is between 1.490 and 1.535 Volts.
To get you to see all this in perspective, I'd abandon all the Intel theories and specs, since we work outside of their spec anyways, and quite a bit so. Let's go by our own findings, they lead to higher OC's!!
