Someone help me please!

hitechjb1 said:

With memory modules using TCCD DRAM chips which would allow a wide range of memory bus frequency

- from low 230 MHz with 2/2.5-2/3-2-10 1T
- to 250 MHz with 2.5-3-3-10 1T
- to possibly 280+ MHz 3-3/4-3-10 1T at 2.x V.
I think 1T is key to good memory bandwidth performance, rule of thumb is 15% leverage over 2T.

Such wide bus frequency range matches the 3000+ CPU overclocking frequency between 2400-2600 MHz for tradeoff under 1T. 3200+ provides slightly overclocking flexibility for matching CPU and memory frequencies.

Memory timings are in this order, tCAS-tRP-tRCD-tRAS.

Set HT_multiplier to x3 during testing of the CPU, so high HTT (above 250 MHz) won't create potential instability from getting HT above 1000 MHz (had x4 been used with HTT 250 MHz or higher). After finalizing CPU overclocking, depending on the actual HTT used, x4 may be used if HTT is under 250 MHz.

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3200+:
In additional to using CPU multiplier x9 as in the 3000+, the x10 provides the following possibility.

max CPU multiplier = x10
CPU to 2400 - 2500 - 2600 - 2700 MHz
HTT (FSB) to 240 - 250 - 260 - 270 MHz

CPU multiplier = x10
memory_FSB_ratio = 1:1 (same as set memory to 200 MHz)
so memory_divider = 10
memory_bus_frequency ~ 240 - 250 - 260 - 270 MHz
memory would run at 2.5/3-3/4-3-10 1T 2.x V

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