possible unlock of superlock procs

[The Coolest]

*BUMP* and...

Well guys, my multi on the fly changing days are over as my motherboard bit the dust (link), and the A7V133s KT133A chipset don't have the FID Command Detect. And although I will give this a shot on the new motherboard, I doubt it will be any different than it was for other people (look in sig for new board).

 

[bulk88]

*BUMP* and...

Well guys, my multi on the fly changing days are over as my motherboard bit the dust (link), and the A7V133s KT133A chipset don't have the FID Command Detect. And although I will give this a shot on the new motherboard, I doubt it will be any different than it was for other people (look in sig for new board).

Some updates, I am NEVER EVER EVER EVER EVER EVER EVER EVER EVER EVER EVER EVER EVER EVVVVVVVVVVVVEEEEEEEEEEEEEEEERRRRRRRRRRRRRRRRRRRRRR again going to blast the new PCB bridges with electricity. Never again. I still say it is a good thing on the old PCB that had exposed bridges, but I will never recommend it be done on a new PCB AMD k7 proc. NEVER AGAIN!!!!! EVER!!!!!!!!!!!! I am so p*ssed.



GRRRRRRR!!!!!

Okay I blasted the 5th L6 bridge, and hisotrically this bridges doesn't like to spark open, there is a 70% chance it will open into a semi-closed state. The bridge doesn't give 0 ohms but gives 4, no electricity goes through it because of the alternative connection inside made. This might be somehow related to the L3 locking. When the bridge has 4 ohms between the sides, the CPU still interprests it as closed. Cutting it won't work and the bridges points still have 4 ohms between them.

I think I superlocked the bridge closed. WTF!????? I dont know how. But that bridge is superlocked.

This isn't guarenteed on the bridges and only has happened to me on the 5th from the "L6" label and it doesn't always happen but 70% of the time it happens. So now this processor is useless for me. Because forever it will have a 12.5x max multi, must get Kt600 board for it and some RAM.

I took another 1.4 duron, did L5 mobile, nicked the L6 bridges and it only took me 10 mins to do. Nicking the L6 bridges is much faster than scraping them and then blowing them. Plus alot less nerve wracking. And nicking works better than blasting cause of the accidently superlocking your proc problem.

I do think it is strange that I internally fused a bridge not at the bridge point but somewhere down the line. This seems to me like as if I super locked it, because even after I did this and throughly cut the bridge, the CPU still read it as closed and my multimeter said it has 4 ohms through the 2 exposed bridge point. Very strange. Maybe one of the guys who tried to unlock L3 should look at my case because I think I figured how AMD locked L3.

 

[Petr]

2 bulk88: Guess why I said in my article not to blow bridges with electricity. Exactly this happened to me, only exception was that the bridge had infinite resistance. But still it was closed to CPU internal logic.

 

[bulk88]

2 bulk88: Guess why I said in my article not to blow bridges with electricity. Exactly this happened to me, only exception was that the bridge had infinite resistance. But still it was closed to CPU internal logic.

I dont take any advice unless it is backed up (soemthing I learned with people screwing me over), if you said the bridge can perminetly fuse close, I wouldn't have done it. Plus I was DEAD scared the first tiem I did it.

 

[Petr]

I dont take any advice unless it is backed up (soemthing I learned with people screwing me over), if you said the bridge can perminetly fuse close, I wouldn't have done it. Plus I was DEAD scared the first tiem I did it.

That was exactly what I said.

 

[bulk88]

I learned of the L5 24x hack. YAHOOO. It allowed me to use a proc I thought i permiently set L6 to 12.5x. Anyways I did a bit of research and found out that the AMD 750, 760, 760 MP, 760MPX will not create the FID signal needed to chagne multiplier. I dont know if it is mandatory (I am think of a way to get around it) to do the signal, but I think atleast on paper (I am no programmer) to get around it.

 

[bulk88]

Wait a sec. I think there is a way to trick the AMD 760 into making that FID_change signal, the singnal is 0007_0002h. Well stop grant is 0012_0002, CPU connect is 0004_0002, halt is 0000_0001. All of these seem to be made by doing
WrLWs command:
SysAddOut: MSB=0 & [33:0] = 1
F8000 0000
SysDatOut: [31:0] = INSERT CODE HERE
EDIT I found out the FID change code from P27 of http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/24319.pdf

and how you do them from P24 of http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/24081.pdf

 

[The Coolest]

What is that code bulk? Can you explain a bit maybe I could help you there.

And what did you do to your chip to get it to work at x24?
I think my ASUS killed my Tbred as well when it died...

 

[Petr]

Well, that code theory is fine, but CPU generates the code, not chipset. Chipset only takes the code, disconnects FSB, changes it's internat FID settings, connects FSB. When chipset doesn't have capabilities to change it's FID settings, then this is going to freeze system, because FID has to be equal to CPU's BP_FID settings.

 

[bulk88]

Well, that code theory is fine, but CPU generates the code, not chipset. Chipset only takes the code, disconnects FSB, changes it's internat FID settings, connects FSB. When chipset doesn't have capabilities to change it's FID settings, then this is going to freeze system, because FID has to be equal to CPU's BP_FID settings.

So the FIDChange is the packet where the new multiper is sent in. I've been looking thorugh all the reserved registers on my 760 (datasheet, set wpcredit to 32bit view mode, 0x0x60, the 60 is the right sided number and the offsets are in 32 bits). I did find and turn on stop grant and halt but that didn't help. I am also using a AMD 761 PCR file that I found on the net, no FID change in it. When I look through the datasheets there is no mention of the chipset NOT supporting powernow, but they do use the word.

Only mention of powernow is here

Power Management Considerations
There are several requirements for BIOS initialization of the
AMD-761 system controller’s configuration register when
supporting power management. Refer to Section 4 on page 185
for further details of these requirements.
For any system enabling the S3 state, a number of core logic
PCI configuration registers and processor MSRs must be saved
or restored prior to suspending or restoring S3. Also, certain
hidden bits must be unmasked. These requirements apply to all
platforms regardless of segment and whether or not AMD
PowerNow!™ is used.

I am think maybe you can change the CPU MSR fields that are put to RAM, then whent eh system resumes the processor will have a new setting.

Also is the phrase "Also, certain hidden bits must be unmasked." Mean that it is in there?

Note: ACPI C3 state is not supported by the AMD-761 system
controller, and the BIOS must not declare C3 support to the
operating system through the Fixed ACPI Description Table.

I thought powernow was APIC S2. Which isn't mentioned anywhere in the datasheet. What is APIC C3?

Currently mucking aropund the BIU registers cause those seem to be the regisatrs that control the cpu. There are some reserved so the is some hope. Also the halt and stop grant enable are located there. There is also an extend BIU with LOTS of reserved, I wonder if I cna write to them.

 

[bulk88]

What is that code bulk? Can you explain a bit maybe I could help you there.

And what did you do to your chip to get it to work at x24?
I think my ASUS killed my Tbred as well when it died...

There are 4 L5 bridges, unknown, Mobile 24x, mobile and multi processor. Well the mobile 24x overides L6 and set the L6 to 24x multplier. No more cutting. Just filling. From now on I wiil take a glob of conductive paste. rub it into all the L5s, let it dry then scrape off the stuff on the surface. When I am done, I have a Athlon maxium 24x transition Mobile MP processor. The mobile mod is much easier now and I will do it to every athlon I have.

 

[bulk88]

teghey-yre 5-hjer-g0e90u9wr8s0ur0i2swu0gu980rww9089890yw0uqwe080y0we8wg8he0eugweuj0pBD

I found the FID change for the AMD 760. And it works.

 

[bulk88]

It is in the extended BIU section. Excerpt from P55 of http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/24081.pdf
Bit Definitions Extended BIU Control (Dev0:F0:0x44)
Bit Name Function
31–11 Reserved Reserved
15–14 Reserved Reserved
10–8 P0_WrDataDly Write Data Delay
P0_WrDataDly is the time in SYSCLK periods from the launch of a SysDC WriteData
command until the launch of the first data object by the processor. This value is a
calculated part of the SIP stream. This value is not provided in the BIU SIP register and is
thus provided here.
7-4 Reserved Reserved
3 P0_2BitPF Two Bit Times Per Frame Enable
This bit enables the use of the two bit time commands on the AMD Athlon™ processor
system bus. This bit must be set when connected to an AMD Athlon processor and
disabled when connected to an Alpha processor. For proper operation, BIOS must not
clear this bit once it has been set.
0 = Two-bit time commands disabled
1 = Two-bit time commands enabled (AMD Athlon processor only
2–0 Reserved Reserved
These bits must be written with 0 (cleared) for normal operation.
Well I set bit 0 to 1. Bit 2 and 1 stay at 0 if a chage them, but bit 0 keeps staying at 1 if a I chage it. You need to change to 32bit view because thats is what I used to find it because that is what the AMD datasheets wrriten in. I dont know the 8bit equivelent. All you need to do is change this one register, nothing else, I am using a Asus A7M266.

YAHOOOOOO. I get credit for discovering something, unlike my quasi credit for the locked xp to mobile unlock hack.

EDIT on
This is for the single processor AMD 761 Northbridge. Not for the Multiprocessing MP or MPX. This might work on them because some of the registars are shared among the 3 but I don't know. Off to a datasheet to figure out if my MSI K7D Master MPX will do it. Unfortuantly I can't test it since I can't take that machine out of service plus it has no Mobiled procs in it.
EDIT off

 

[bulk88]

My mother jsut scolded me as being AMD's biggest threat. She told me not to give out the AMD760 FID register, well I did. Am I going to cause AMD to go bankrupt?

 

[bulk88]

The MPX does have the same 3 reserved bits at the same address in. So the MPX also proably supports it but I cant test it. No clue about AMD 750 (if that ever came in socket A).

 

[Petr]

It is bit 0 of register 44h. Thanks!

Don't you want to be the second most famous in this unlocking effort (after me )? You have nForce 2, I know the bit that should enable FID_Change... just it doesn't work. Find solution and you will be king.

 

[stamasd]

Beware of the AMD hit squads though.

 

[bulk88]

It is bit 0 of register 44h. Thanks!

Don't you want to be the second most famous in this unlocking effort (after me )? You have nForce 2, I know the bit that should enable FID_Change... just it doesn't work. Find solution and you will be king.

I had the datasheets to help me find reserved registers and narrow it down to the BIU class. With NF2 everything is effectivly reserved and unknown. Someone said they would release a PCR for NF2 (even NF1 would be helpful), and that would narrow it down tremendiously. There is no starting point with NF2, I am thinking you need to enable some other cycle or power managment mode in NF2.

 

[ElrOnD]

bulk88

So, is it possible to use your method of unlocking in NF2 mobos?
Specially in NF7?

[]z

 

[bulk88]

bulk88

So, is it possible to use your method of unlocking in NF2 mobos?
Specially in NF7?

[]z

LOL

I have an NF7-S V2, heck I am typing this msg from it. It would be cool, but I cant play with this system, it is too important if it fails. If I get another NF2 I will try to find it. I discovered that you can convert a locked xp into a mobile then using power increase the multiplier, I didn't discover power now, but I am the first or one of the first to try it on a locked proc, seeing your Duron 1.4s planning to go into a SMP board and no multiplier and no decent overclocking via FSB makes me enough to do anything. I even distroyed 3 durons doing these mods (2 1.4s and 1 1.6) initially. I also 100% guarenteed discovered how to turn on Poernow support in the AMD 760 chipset.