PCI Chipset Modifier

Add Your Comments

A handy little program to change any PCI settings — Bill Lane

DESCRIPTION:

This program will allow for the modification of a doubleword
at any arbitrary device #, bus #, function # and offset in the
PCI configuration space. It could be used to setup hidden BIOS
settings or change PCI latency timers on any device.

This utility is not particularly user-friendly.

The command-line parameters must be entered as follows:

pcimod -dD (single digit) -bB (single digit) -fF (single digit)
-oO (0xhex value of offset) 0x (dword value to be written in HEX!)

The dD parameter is a decimal number specifying the device number,
the bB parameter is a decimal number specifying the bus number, the
fF parameter is a decimal number specifying the function number, the
oO parameter specifies the offset. Note the offset is a dword
value in hex and MUST be a multiple of 4. The last parameter 0x
is the new dword-value (in HEX) you would like to write to the
specified device number, bus number, offset and function number.

USAGE NOTES:

I’ve only tested this utility on two different VIA MVP3 based systems
under Windows 98. It worked on both these systems.

The utility can be run from a DOS box while in windows 95/98. It would be
better to run it from an autoexec.bat file before you enter Windows 98 —
especially if you mess around cache settings.

If you don’t have datasheets for your motherboard’s chipset or vid-card, this utility won’t do much for you.

You need to know in advance what you
want to change (i.e. the device#, bus#, function# and offset of the doubleword you want to modify) and what you don’t want to change. Then check, re-check and write-down the original doubleword value at the device#, bus#, function# and offset you plan to modify and OR this value w/the values you want written.

PCImod will not work under Windows NT or Windows 2000.

PCImod can instantly lock up your system.

A hard-reset cleared this problem for me, but it’s possible you may have to restore your BIOS to its defaults. Since any Read/Write register in the PCI configuration space can be written to (including the BIOS and any expansion cards), it’s possible to cause a lot of problems if you don’t know what you’re doing.

I’ve personally been using this utility on two MVP3-based systems (a K6B3+
and a VA503+) to:

  1. Enable SDRAM bank-interleave (K6Bv3+)
  2. Enable read-around-write and DRAM read pipeline (K6bv3+)
  3. Enable PCI Master Bus Timeout (which prevents any PCI device from grabbing the PCI bus for more than a specified number of clks (in this case, 128).

This utility would (like H. Oda’s WPCREDIT) work for any PCI device
w/RW (readable/writable) registers.

EXAMPLES (for a MVP3-based DFI K6bv3+):

1) pcimod -d0 -b0 -f0 -o0x50 Reports back the doubleword at offset 50h

2) pcimod -d0 -b0 -f0 -o0x50 0x30050390

Sets the doubleword for device 0, bus 0, function 0, offset 50h to
30050390h (NOTE: the original value for this offset is 00050380h)

The registers set up the following for device 0, bus 0, function 0 and
offset 50h:

for register 50: 90h cache enable and tag configuration
for register 51: 03h L2 cache control
for register 52: 05H more L2 cache control
for register 53: 30H my mod enable cache write pipe & DRAM read pipe

Note how the doubleword 30050390 corresponds to the registers:

Register 53

Register 52

Register 51

Register 50

30

05

03

90

3) pcimod -d0 -b0 -f0 -o0x74 0x00c08480 Sets the doubleword for device 0, bus 0, function 0, offset 74h to
00c08480h (NOTE: the original value for this offset is 00c08080h)

The registers set up the following:

for register 74: 80 PCI master read prefetch and write merge control
for register 75: 84 PCI arbitration1 mod force arbitration after 128clks
for register 76: c0 PCI arbitrtion2
for register 77: 00 no function

USAGE NOTES FOR KT133/KT133A/KT133E CHIPSETS TO ENABLE 4-WAY INTERLEAVE

My Chaintech AJA2E motherboard has SDRAM bank interleave disabled by default and there is no way to turn it on. Since it is based on the KT133E chipset, you can use PCImod to turn on 4-way bank interleave. We simply change the value for device 0, bus 0, function 0, offset 64h, 65h, 66h and (maybe) 67h. Each one of these offsets controls two banks of SDRAM. Since my AJA2e only implements banks 0,1,2,3,4,5 only 64h, 65h and 66h have to be modified.

Simply invoke PCImod as follows to turn on 4-way bank interleave for banks 0, 1, 2:

  • rem turns on 4-way bank interleave
  • rem default is c4e4e4e4h
  • pcimod -d0 -b0 -f0 -o0x64 0xc4e6e6e6

What we’re doing here is turning on bit one and turning off bit zero. These are the bits which control bank interleave. If these bits are 00, interleave is off (which is the default). If the bits are 01, interleave is 2-way and 10 is 4-way interleave. What I’m doing is OR’ing 02H with the LSB of each control register. Here are the complete settings for each register in detail:

Bit Number

Function Values

7

Precharge command to active command period 0 Trp = 2T
Trp = 3T – default

6

Active command to precharge command period 0 Tras = 5t
1 Tras = 6t – default

5-4

CAS latency 00 1T
01 2T
10 3T – default
11 reserved

3

DIMM type 0 standard
1 registered – default

2

SDRAM: active command to CMD command 0 2T
1 3T – default

2

VCM SDRAM: prefetch read latency 0 4T
1 3T

1-0

Bank Interleave 00 no interleave – default
01 2-way
10 4-way
11 reserved

I’ve got a similar fix for MVP3-based motherboard for enabling bank interleave.

BUG REPORTS:

If you notice any problems please give me the output of PCImod as a text
file. You would do this by invoking the program something like this:

pcimod -d0 -b0 -f0 -o0x74 0x00c08480 >> pcimod.txt

RESPECTS/THANKS TO:

Jari Korhonen
parru@mbnet.fi
http://koti.mbnet.fi/parru/
author of the original PCI latency utility: latency.exe.

P.S. If anyone out there has the datasheets for the VIA KT133 chipset or Nvidia GeForce 2/GTS chipset I would appreciate a copy.

ver 1.0 5/19/02
Last changed 5/19/2002 by
Bill Lane

DOWNLOAD PCI Mod (10K)

Leave a Reply

Your email address will not be published. Required fields are marked *