• Welcome to Overclockers Forums! Join us to reply in threads, receive reduced ads, and to customize your site experience!

3770K IHS removal and results

Overclockers is supported by our readers. When you click a link to make a purchase, we may earn a commission. Learn More.

graysky

Member
Joined
May 6, 2007
PART 1
Introduction
Feeling somewhat curious about the reports that inferior Thermal Interface Material (TIM) ships from the factory inside Ivy Bridge (IB) chips, I found myself taking my new 3770K out of the safety of its socket this afternoon and on to my desk where it went under the knife. About 15 min later, I finalized the divorce of its Internal Heat Spreader (IHS) and its Printed Circuit Board (PCB). It was surprisingly simple to do; a standard razor blade (0.009") and a little bit of patience was all that was required. After cleanup and application of fresh TIM, I sought to put a nice story together for you readers covering how to do procedure yourself and sharing my results and the methods used to arrive at them.

Removing the IHS from an i7-3770K
Maintain a level blade and gently insert it between the green part of the chip (PCB), and the silver part (IHS). I found it best to start on a corner. From what I've read, care needs to be taken not to scrap the PCB, as key parts of the chip reside very close to the surface. Slowly and gently, rock the blade between the two until it penetrates. Then slide it around the perimeter. See the pics to visualize the die so you don't push the blade in too far. The IHS will come off easily once you have completed severing the glue which is removed with gentle scraping with credit card or finger nails; isopropyl alcohol doesn't help much. When finished cleaning up both pieces, apply TIM to the die, place it back in the MB, and gently place the IHS on it. Lock it into place in the MB with the mounting bracket that will hold the IHS to the chip securely thus keeping you from having to glue down the IHS.

image.jpg
cut_2.jpg
pretty.jpg

I'm a pretty big fan of Arctic Silver 5 (AS5) and used it both on the die, and on the outside of the IHS. My "factory" configuration had a good 120 h of load/idle cycles on it. As you probably know, AS5 has a breakin period associated with it...200 h according to Arctic Silver Incorporated. One can argue that this claim is valid based on the delta temp data.

Data Collection and Analysis
I wanted to generate robust and statically valid conclusions about the efficiency of entire process; results are drawn from a fairly large data set looking at the populations of temperatures and VID values. Temps and vcore values were collected via lm-sensors driven by a simple shell script which queried it every 2 sec logging the results to a file (see the end of this section for the script).

Example:
Code:
dts,vcc,temp,core0,core1,core2,core3,120mm_rpm,120mm_pwm,140mm_rpm,140mm_pwm
07-28-12 09:19:31 AM,1.280,66.0,58.0,63.0,65.0,60.0,1285,255,1225,255
07-28-12 09:19:34 AM,1.272,65.0,57.0,62.0,65.0,61.0,1300,255,1216,255
07-28-12 09:19:36 AM,1.272,64.0,59.0,63.0,66.0,59.0,1294,255,1226,255
...

These data were annotated and distributions were analyzed to see if the different TIMs under the IHS really makes a difference. Note that there are too many variable to control for this sort of analysis to be 100 % iron clad. For example, TIM spreading variations, mounting techniques, variations in hardware, etc. Even room temp can't be rigorously controlled. My office is air conditioned and ranged from 75-77 F when I ran the stress tests. In retrospect, I would have located the PC in my basement which has very consistent ambient temps but hind sight is always 20/20!

Methods of Stressing
I use linux, but key stress testers are cross platform. Intel BurnTest for windows is based on linpack from Intel which is available for many platforms. The settings I used were 25k problem sizes and 25k leading dimensions with 4 KB alignment.

On top of linpack, I ran a compile job looped in the background (nice=19) set to use 8 threads to further scarfs-up any unused CPU cycles.

System Specs and Settings
Asus P8Z77-V Pro
Intel 3770K @ 45x100
Cooling is an NH-D14 with both fans; my system manages their speed but they are both running on max for the stress tests (1,200 RPM for the 140mm and 1,300 RPM for the 120mm).

The BIOS is running using a vcore in offset mode so the vcore is automatically controlled by the BIOS and is dependent on load. Mine is stable with a setting of +0.0200 and here are the other key voltages and settings in case you're wondering:
Code:
VCCSA Voltage = 0.92500
CPU PLL Voltage = 1.5500
PCH Voltage = 1.06000
CPU Load-Line Calibration = Ultra High
CPU Current Capability = 140 %
CPU Power Response = Medium

Results
I ran the stress test described above for ~2 h period and used the geometric mean of the temps per core as the "average" temperature over that time period. I repeated this for a total of 4 nights, but lost the data on day 1 due to an overwrite on my part! Here are the average corresponding temps per day; there is a nice decrease out to day 3 where it more or less plateaus off. Perhaps that is the AS5 "breaking-in." Also note the error bars correspond to the measured ambient temp which ranged between 75-77 F or 1.1 C. You can see that some values at day 3 and 4 are not different when accounting for this:
temps.jpg

As well, here is a plot of the delta temp, that is, the values subtracted from the stock results indicating the magnitude of temperature decrease:
delta_T.jpg

And to be sure this horse has been beaten well after it died, here are the results compiled in a table:
table.jpg

Conclusion
For this example, a decrease in load temps was observed after delidding an Intel 3770K and replacing the factory TIM with AS5. The magnitude of the temperature reduction was not even across all cores, and ranged for -2C to -12C. The data are consistent with Arctic Silver Inc.'s claim that the TIM requires a break in period. This has to be one of the cheapest modifications to gain lower operating temperatures which can be converted into higher voltage and likely higher clock rates. The unevenness of the decrease is puzzling. Since the overall rank order of temps was retained after the TIM replacement, perhaps it has to do with some physical unevenness in the IHS, in the base of the HS, or on the CPU die itself. Investigating this is beyond the scope of this exercise.

Supporting Data
Link to my shell used to log the data.
Link to my shell script used to run gcc in the background.
Link to the entire data file (tab separated) should you wish to dig into it.

PART 2
Introduction
The above analysis was conducted using both a non-lapped IHS on the CPU and a non-lapped heatsink. I have since lapped both parts and repeated the experiment. My results seem to confirm that lapping these CPUs give minimal albeit real benefits. Others have reported no gains.

Lapping Parts
The process of lapping in detail will not be reviewed here, but in summary, one uses wet/dry sandpaper and a flat surface (glass usually) to slowly and iteratively grind an uneven surface. The goal of lapping is not be to make a mirror surface, rather, it is to make flat surface.

Lapping setup:
lapping.jpg

Heatsink lapping (220 grit --> 320 grit --> 400 grit --> 800 grit --> 1000 grit). Read this composite pic from left-to-right and from top-to-bottom:
heatsink.jpg

As evident in the photos, the base of the NH-D14 is actually quite flat from the factory.

IHS lapping ( 400 grit --> 800 grit --> 1000 grit). Read this composite pic from left-to-right and from top-to-bottom:
lapped_cpu.jpg

As evident in the photos, the IHS on this 3770K was quite concave, that is, higher in the middle than elsewhere. "Flatness" was achieved in this case when no more silver color remained on the IHS.

Stress Testing
In addition to the linpack+gcc method described above, mprime (this is the linux version of prime95) running large FFTs was coupled with the same gcc compile stress to give another endpoint. By default, mprime runs with a background nice level (nice=19) and gcc ran with priority (nice=10). This is in contrast to the linpack+gcc setup where linpack ran with a higher priority and gcc ran with a background priority. This was by design.

In the linpack stress, gcc was employed to add further stress since linpack does not stress all cores evenly during a given run. In contrast, mprime does a very efficient job leveling load across all cores for a given calculation. Here gcc was given priority over mprime since the very nature of compiling code will lead to uneven usage.

Results
Rather than showing a per-core analysis which would make for a rather busy graph (4 cores x 2 conditions), a more simplistic "Lapped" and "Non-lapped" average results across all 4 cores is shown for each of the stress methods:
results.jpg

The delta temp spread for the averaged results ranged from 0 to -9 for the mprime+gcc experiments and from -1 to -12 for the linpack+gcc experiments.

Each line is relate to the factory TIM/unlapped result represented by the y=0 dashed black line. Again, these are delta temps which are relative to that factory result. The pink line shows the average drop in temp across all 4 cores for the unlapped results while the blue line shows the average drop in temps across all 4 cores for the lapped IHS and for the lapped HS. The data show a real but trivial difference after lapping both parts for most days. The exception being in the linpack+gcc stress on day 3. Here the average deltas are within error of each other based solely on the fluctuation in ambient temp.

Conclusion
Based on these data, lapping an i7-3370K and the heatsink used to cool it produces minimal benefits in heat dissipation gains.
 
Last edited:

Knufire

Senior Member
Joined
Feb 17, 2010
Location
Manassas, VA
Did you ever unmount and check your TIM application after the tests? It could be that the TIM didn't spread evenly across all the cores, causing the huge differential in the deltas.

Either way, this is a great writeup! Many of us wouldn't have the guts to delid an expensive CPU like this, but great data! :)
 

bmwbaxter

Joined
Jun 9, 2010
Great read! I like seeing independent investigations of stuff like this. I especially like how open and from my brief review seems to be up to par. :thup: for having the guts to delid!
 
OP
G

graysky

Member
Joined
May 6, 2007
Did you ever unmount and check your TIM application after the tests? It could be that the TIM didn't spread evenly across all the cores, causing the huge differential in the deltas.

A total of 4 times actually. I have since lapped the IHS and will post if there is a difference there.
 

OneArmedScissor

Member
Joined
Mar 15, 2006
A total of 4 times actually. I have since lapped the IHS and will post if there is a difference there.

Same here. I have a i5 3570k and I've reapplied the thermal paste goop three times already and my temps still vary by a big deal between the cores.
 

E<>MC^2

New Member
Joined
Jul 29, 2012
Could put Ivy Bridge back into the running

The use of TIM inside a package reminds be of the Sony PS3 RSX graphics / memory chip module problem with YLOD. Briefly, after several years, the TIM degrades and the chip overheats and self destructs or un-solders itself. This is the reason for the failure of many early fatter PS3 units. Some businesses sprang up to re-solder the broken PS3 units and install AS5 inside the chip modules.

IMHO Intel intends to increase profits by using TIM.

I have no proof, but am suspicious that the use of TIM will make the chips have a lifetime shorter than the same chip if the heat spreader was soldered.

Though I had great initial expectations, the heat up issue made me hold off on getting an Ivy Bridge setup.

This thread opens the door to users that want to better utilize Ivy Bridge CPUs. Although risky to open and work inside chips, we now know there is a path to improve the chips ourselves, and maybe make them last longer, run faster, and be able to re-apply the AS5 TIM to keep the chips from degrading and dying the way the original PS3 units did.

Thank you very much for the excellent information Graysky.

Please tell us more about the details of applying the AS5.
 

bmwbaxter

Joined
Jun 9, 2010
The use of TIM inside a package reminds be of the Sony PS3 RSX graphics / memory chip module problem with YLOD. Briefly, after several years, the TIM degrades and the chip overheats and self destructs or un-solders itself. This is the reason for the failure of many early fatter PS3 units. Some businesses sprang up to re-solder the broken PS3 units and install AS5 inside the chip modules.

IMHO Intel intends to increase profits by using TIM.

I have no proof, but am suspicious that the use of TIM will make the chips have a lifetime shorter than the same chip if the heat spreader was soldered.

Though I had great initial expectations, the heat up issue made me hold off on getting an Ivy Bridge setup.

This thread opens the door to users that want to better utilize Ivy Bridge CPUs. Although risky to open and work inside chips, we now know there is a path to improve the chips ourselves, and maybe make them last longer, run faster, and be able to re-apply the AS5 TIM to keep the chips from degrading and dying the way the original PS3 units did.

Thank you very much for the excellent information Graysky.

Please tell us more about the details of applying the AS5.

The use of TIM vs. Solder won't make a difference on the life of the chip. Before intel started soldering the die to IHS there was lots chips used TIM. There are plenty of chips running for 10+ years with TIM. Since Intel hasn't said anything it is unfair to say that intel didn't solder the chips just to save money. There maybe something else which may have to do with the 22nm fab or tri gate transistors... etc. Just playing devils(intel's) advocate here.

but IMO intel used TIM to cut costs and boost profit.
 

Woomack

Benching Team Leader
Joined
Jan 2, 2005
My cpu with MX4 has still +/-4*C difference between cores and I checked TIM couple of times. Cooling ... box cooler so far ;) ... one thing that I forgot to make is to check temps before I removed IHS so now it's hard to compare :p
 

E<>MC^2

New Member
Joined
Jul 29, 2012
It's not the TIM, my IHS is concave.

I wonder if the void filling Indigo-Xtreme system, which is optimum outside the IHS would be "void filling" candidate for a concave surface inside the IHS.

Lot of products to chose from. Intel knows best and has made chips with the cheaper TIM before, but isn't giving us a choice for Ivy Bridge yet. Maybe we should start screaming about this.

Intel's patent number 7009289 for flux-less solder uses Gold / Tin compound under the IHS cover, and reflow (heat) with metalization on the wafer backside (chip). I can't tell if the Ivy Bridge chip backside is metalized from the photo above.

Expensive Gold is needed for "flux-less" soldering. There is good reason to believe it saves Intel money when they use TIM paste instead instead of soldering the IHS. I have an Intel CPU with TIM paste inside that was overclocked for more than a year. The chip temperature now runs hotter than it first did, which is pretty good evidence that the TIM paste degraded. Degraded means the paste conducts less heat as it ages.

Indigo-Xtreme is a low temperature metallic reflow. It costs about $10 per use and isn't good for mass production like Intel's patented method, though it may be good to improve the current crop of Ivy Bridge chips heat conduction, maybe better than the AS5 and MX4 mentioned in this thread already.

If someone tries Indigo-Extreme under the IHS, they might want to tack glue the IHS rather than the un-glued approach described here, in order to keep the void filler in alignment with the chip.
 
Last edited:

manu2b

Member
Joined
Feb 6, 2011
@Woomack: what is the temp drop for you by changing the TIM between the die and the IHS?

EDIT: I am leaning toward a 3770k on a m-ATX board (so no WC), but these temps...
 

Woomack

Benching Team Leader
Joined
Jan 2, 2005
@Woomack: what is the temp drop for you by changing the TIM between the die and the IHS?

EDIT: I am leaning toward a 3770k on a m-ATX board (so no WC), but these temps...

as I already said I forgot to check what temps I had on stock TIM before I removed IHS :bang head

I will test it on SS soon so I will see if there is any improvement in overclocking. Results that I saw in the web are showing about +100MHz better oc because of temp drop.
I also saw that when SS had 4-5*C higher temp then my cpu was overclocking ~100MHz worse so I would be happy with even small difference.
 

xander89

Member
Joined
Apr 11, 2010
Location
London, UK
as I already said I forgot to check what temps I had on stock TIM before I removed IHS :bang head

I will test it on SS soon so I will see if there is any improvement in overclocking. Results that I saw in the web are showing about +100MHz better oc because of temp drop.
I also saw that when SS had 4-5*C higher temp then my cpu was overclocking ~100MHz worse so I would be happy with even small difference.

I've seen as much as a 15/20c drop with colab liquid pro. Seems like the one to use if you really want to bring those temps down. I'm trying to dig out where i saw it. The bloke managed to hit 4.9ghz with about 80c load :attn:

This guy got a 28c drop with colab liquid pro and a 16c drop over as5 :O

http://www.overclock.net/t/1283797/ivy-bridge-3770k-de-lid-liquid-pro-as-5-tested-amazing-results

Thats not the original one i found, but ive seen it alot, that colab liquid pro gets BY FAR the best results with IHS removal! Almost so much so that when i have £250 to throw away I might grab myself a 3770k and go for 5ghz ;)
 
Last edited:

Woomack

Benching Team Leader
Joined
Jan 2, 2005
I've seen as much as a 15/20c drop with colab liquid pro. Seems like the one to use if you really want to bring those temps down. I'm trying to dig out where i saw it. The bloke managed to hit 4.9ghz with about 80c load :attn:

I saw up to 12C with CLP and I could use it but ... do you know how it will be acting after lets say a year ? So far I used MX4 and I'm looking for more tests. I think I will add CLP to some other order just don't know when ( don't want to pay $10 shipping costs for TIM worth $15 :p ).
I'm almost only using SS on this cpu and from time to time stock cooler when I'm testing something for longer and I don't need high cpu clock ( SS is kinda loud ).

Thanks for the link. I had ~75*C on 1.2V and box cooler so maybe it's not that bad ;)
Will test some more when I finish reviews.
 

xander89

Member
Joined
Apr 11, 2010
Location
London, UK
I saw up to 12C with CLP and I could use it but ... do you know how it will be acting after lets say a year ? So far I used MX4 and I'm looking for more tests. I think I will add CLP to some other order just don't know when ( don't want to pay $10 shipping costs for TIM worth $15 :p ).
I'm almost only using SS on this cpu and from time to time stock cooler when I'm testing something for longer and I don't need high cpu clock ( SS is kinda loud ).

Thanks for the link. I had ~75*C on 1.2V and box cooler so maybe it's not that bad ;)
Will test some more when I finish reviews.

i assumed the CLP would be orite after a year. i swear its only aluminium it eats through? The copper and nickle on the ISH shouldnt have any issues. Does anyone know what material the surface of the core actually is?
 

xander89

Member
Joined
Apr 11, 2010
Location
London, UK
hmmm if it is then clp shouldnt have any issues. It seems like the clear winner, seen people get some killer results with it!