Good News/Bad News
The good news is that the AthlonMP is compatible with socket A system, the bad news for the impatient is that it won’t work properly unless it gets a bios update and only the A7V133 (which recently got a BIOS update for “H Series” Athlons) has this in place right now.
The good news is that the AthlonMP is relatively cheap for a server chip. The bad news is that it’s more expensive than current TBirds, and doesn’t have any obvious benefit like a larger cache (at least not according to AMD’s techdoc on the new processor
The good news is that the AthlonMP does perform a bit better than the TBird. The bad news is 5% is roughly the average gain you’ll see. (SMP operations are likely to see more improvement).
Now AMD never said Palomino would do a lot better than TBird clock-for-clock, quite the opposite, as a matter of fact. Back in January, Jerry Sanders said Palomino would do just a little better, so it’s not like they didn’t tell us.
The good news is that the AthlonMP does chew up less power. The bad news is at the speeds and voltages overclockers will be using, it’ll be right back to the furnace.
The bad news is that it will all be done at 1.75V, not 1.4V or so as expected.
While this isn’t bad news per se, if you extrapolate the number, you can see where we’ll be shortly.
(I don’t honestly think now that 2000Mhz is going to be a realistic goal with these processors as is without extreme measures).
The good news is that TBirds work fine in SMP mode. The bad news is you’re going to need one hell of a cooling solution to keep two furnaces fairly cool.
The good news is that one day, we’ll have relatively cheap SMP boards. The bad news is, probably not for at least a few months.
What about overclocking?
I went through the documentation for the AthlonMP (officially known as the Model 6 Athlon, as opposed to the TBird’s Model 4), and there is very little change in
the documentation and pin count. All the TBird pins involved with overclocking are still there.
The only real change in the pin structure is setting a couple pins aside for thermal monitoring and protection. Other than that, it looks to be the same.
There are no changes to the voltage and multiplier values; it’s just the same as a TBird.
When we first got a look at the Palomino, there were a lot more bridges, and the number of bridges upon which pencil jobs were performed increased from four to five.
I honestly don’t know what a lot of these bridges are for, but there sure doesn’t seem to a bunch more things this processor does compared to a TBird. My best guess is that this is mostly a manufacturing move, and may
might give AMD the option to enable or disable certain functions (like SMP) in the future.
Why the extra L1 bridge? I don’t have the processor here, and can’t test for it, but I suspect I know what it may be.
Remember those thermal pins? They’re located in the general vicinity of the FID pins. I would bet that fifth bridge is the link between any thermal signal and the motherboard.
Could be completely wrong, and if all the necessary bridges are closed, the point is moot anyway, but anybody who has one might want to look into that.
Palomino will be a somewhat cooler version of a TBird able to run at somewhat higher speeds than a TBird. It’s an evolutionary, not revolutionary CPU; it’s much more similiar than different from a TBird. Sorry.
If you demand a revolution before you buy, then go to sleep at least until Willy2 shows up (though that is likely to disappoint revolutionaries, too). Realistically, the next big jump is going to be Clawhammer sometime in 2002.