Deliberate Confusion?

So we have one processor family with two rather different processors in it. The Clawhammer type has 754 pins, the Sledgehammer type has 940.

This is going to cause huge confusion. When AMD says, “the Opteron will do or have ______” does that mean all three of the abovementioned will? Or just items
two and three? Or just item three?

This fudging could hide much, and is especially bad for those of us interested in item number one. When they talk about Opterons, does it apply to
the processor we plan to buy or not?

Dual or Not?

Let’s just provide what should be one simple example. What whats support dual channel DDR? By the time Athleron, or whatever the hell they call the Opteron That Is But Isn’t come out, we’ll have PIV dual-channel boards. The competition will have it, will this?

If I look here, it says, “As we know, ClawHammer features a 64-bit memory interface, while the high-end SledgeHammer has a 128-bit memory interface.” That’s apparently what AMD said at IDF. Unless there’s some mysterious quad-pumping going on which AMD hasn’t mentioned, that seems to indicate no dual-channel for a 64-bit whatever.

This seems to be confirmed by page 14 of the AMD Opteron presentation, which says, “Dual channel DDR memory interface (128-bit bus) gives up to 8.4GB/s (PC2100 DDR) or 10.8GB/s (PC2700 DDR) on dual processing with AMD Opteron processors (900-pin) . . . . (The AMD diagrams show two dual DDR channels, one for each processor, that’s why the figures are double what you’d expect.)

This seems to indicate that you need 128-bit memory bandwidth to have dual DDR channels, and only Sledgehammer has it.

On the other hand, we have this statement in the middle of a discussion of a Clawhammer board which says, “Support will be provided for both single and dual channel DDR memory interface for up to 5.3GB/sec of memory bandwidth when using DDR2700.”

For this particular motherboard? For Clawhammers? For only certain kinds of Clawhammers? Was that comment just meant for Sledgehammers? I don’t know.

Are we going to have to go through this on every damn feature of these chips?

From several sources, we hear that the Clawhammer Athlon can only handle two memory chips. Sledgehammer can handle lots. There’s maybe some indications the Opteron Clawhammer can handle more than the Athlon Clawhammer. Maybe. I’m not sure.

Is the Clawhammer we’ve been waiting for the next XP, or the Duron of the X86-64 family? I don’t know, but I’m leaning to the latter.

All these items could have easily been spelled out in the background information provided along with the presentation. It wasn’t. That makes me wonder. A lot. And not positively.

If they hadn’t gone into technical details at all, I wouldn’t be complaining. The problem is they created an inherently confusing situation, and then half-explained it.

It’s All In The Latency?

This level of confusion makes you question items that maybe shouldn’t even be questioned.

Perhaps the most important piece of news yesterday was the revelation that almost all of the new chip’s performance comes from an integrated memory controller: 20% of the 25% improvement. In short, this is an Athlon with some 64-bit bits and SuperController.

I suppose it’s conceivable, but I’d sure like to see it.

However, with all this vague talk of Opterons and not-so-Opterons, I have to wonder whether that 20% improvement is due to the memory controller per se or just due to dual channel DDR.

Remember, they talked about Opterons yesterday, and the uniprocessor Clawhammer isn’t going to be an Opteron, it’s going to be an Athlon. Maybe it applies, maybe it doesn’t.

Could I be wrong on this? Sure. But when your organization is known for being slick in its pronouncements, and your presentation is essentially loophole heaven when it comes to the low-end, I want everything spelled out before I lay out my money.

And so should you, else you may end up buying the wrong processor for what you want to do.

Ed