A64 CPUs, chipsets, motherboards

[hitechjb1]

What are some of the differences between revisions E3, E4 and E6

The E3 Venice ends with BP in the OPN code, whereas the E6 Venice ends with BW.
E.g.
Desktop A64 939 (90 nm SOI DSL) Venice
Rev E3 Venice
3000+: ADA3000DAA4BP 1.35/1.4V (DH E3 rev, 00020FF0h) Venice, 512 KB L2, 1.8 GHz, x9, 67 W
3200+: ADA3200DAA4BP 1.35/1.4V (DH E3 rev, 00020FF0h) Venice, 512 KB L2, 2.0 GHz, x10, 67 W
3500+: ADA3500DAA4BP 1.35/1.4V (DH E3 rev, 00020FF0h) Venice, 512 KB L2, 2.2 GHz, x11, 67 W
3800+: ADA3800DAA4BP 1.35/1.4V (DH E3 rev, 00020FF0h) Venice, 512 KB L2, 2.4 GHz, x12, 89 W
Rev E6 Venice
3000+: ADA3000DAA4BW 1.35/1.4V (DH E6 rev, 00020FF2h) Venice, 512 KB L2, 1.8 GHz, x9, 67 W
3200+: ADA3200DAA4BW 1.35/1.4V (DH E6 rev, 00020FF2h) Venice, 512 KB L2, 2.0 GHz, x10, 67 W
3500+: ADA3500DAA4BW 1.35/1.4V (DH E6 rev, 00020FF2h) Venice, 512 KB L2, 2.2 GHz, x11, 67 W
3800+: ADA3800DAA4BW 1.35/1.4V (DH E6 rev, 00020FF2h) Venice, 512 KB L2, 2.4 GHz, x12, 89 W
...
E.g. as of 0508, the 5-letter stepping:
CBBLE (Venice E3)
LBBLE (Venice E3)
YBBLE (Venice E3)
LBBWE (Venice E6)
...

Other E4 such as FX and Manchster, E6 such as Toledo are
E.g.
Desktop A64 X2 939 (90 nm SOI DSL) Toledo
3800+: ADA3800DAA5CD 1.35/1.4V (JH E6 rev, 00020F32h) Toledo, 2x 512 KB L2, 2.0 GHz, x10, 89 W (512 KB L2 per core "disabled")
4400+: ADA4400DAA6CD 1.35/1.4V (JH E6 rev, 00020F32h) Toledo, 2x 1 MB L2, 2.2 GHz, x11, 110 W
4800+: ADA4800DAA6CD 1.35/1.4V (JH E6 rev, 00020F32h) Toledo, 2x 1 MB L2, 2.4 GHz, x12, 110 W

Desktop A64 X2 939 (90 nm SOI DSL) Manchester
3800+: ADA3800DAA5BV 1.35/1.4V (BH E4 rev, 00020FB1h) Manchester, 2x 512 KB L2, 2.0 GHz, x10, 89 W
4200+: ADA4200DAA5BV 1.35/1.4V (BH E4 rev, 00020FB1h) Manchester, 2x 512 KB L2, 2.2 GHz, x11, 89 W
4600+: ADA4600DAA5BV 1.35/1.4V (BH E4 rev, 00020FB1h) Manchester, 2x 512 KB L2, 2.4 GHz, x12, 89 W

Desktop A64 939 (90 nm SOI DSL) San Diego
3500+: ADA3500DAA4BN 1.35/1.4V (SH E4 rev, 00020F71h) SanDiego, 512 KB L2, 2.2 GHz, x11, 67 W (512 KB L2 "disabled")
3700+: ADA3700DAA5BN 1.35/1.4V (SH E4 rev, 00020F71h) SanDiego, 1 MB L2, 2.2 GHz, x11, 89 W
4000+: ADA4000DAA5BN 1.35/1.4V (SH E4 rev, 00020F71h) SanDiego, 1 MB L2, 2.4 GHz, x12, 89 W


From an AMD tech doc, the differences between
E3 (DH-E3 Venice) on one hand,
E4 (SH-E4 FX, BH-E4 Manchester) and
E6 (includes DH-E6 Venice and JH-E6 Toledo) on the other,
are Erratum 113, 114 and 116.

E3 had the erratum 113, 114 and 116,
the SH-E4 (FX), BH-E4 (Manchester) and the DH-E6 (Venice), JH-E6 (Toledo) have them fixed.

The BH-E4, JH-E6 now have the Erratum 123 and 124 (for dual core).

For details about the various erratum, refer to the AMD tech doc 25759.

113 Enhanced Write-Combining Feature Causes System Hang

114 DDR Data Pin Drive Strength Also Affects Command/Address Pins

116 DDR Chip Selects Tristated One Clock Early in Power Down Mode

...

123 Bypassed Reads May Cause Data Corruption or System Hang in Dual Core Processors

124 STPCLK Throttling Causes Violation of VDD_ac Specification on Some Dual-Core Processors

The two errata 123 and 124 are documented in this AMD tech doc 25759, page 80 and 81 respectively.

Further, these errata 123 and 124 for the E4 and E6 reveisions are logical changes and fixes, so IMO (not supported by actual data), the overclockability of these different revisions per core, which is mainly determined by the physical circuits, transistor properties and manufacturing process, should be about the same for these different revisions, except the normal variability presented among the silicon wafers over time.

DH-E3 had these three 113, 114, 116 erratum, and
the newer revisions such as SH-E4, BH-E4, SH-E5, DH-E6 and JH-E6 have them fixed.


Dual core overclockability is related to its associated single core like this.
Dual core overclocking estimation from single core statistic

A64 940, 754, 939 CPU Models, OPN code, rating

Revisions and steppings

How to identify the physical core of an A64 (post 86)

 

[EternalX]

good info!

 

[RotKT]

thanks

 

[wizard james]

ahhhhhhhhhhhhhhhhhhhhh

 

[rseven]

I don't know how I have spent the thousands of hours I have spent in the Forum and not noticed this thread. Hitechjb1, this thing is a regular A64 thesis! What an amazing job filled with all kinds of things I didn't know but was curious about. Many thanks to you and two thumbs up!

 

[hitechjb1]

Added FX-60, an A64 90 nm socket 939 Toledo based dual core processor.

FX-60: ADAFX60DAA6CD 1.35/1.4V (JH E6 rev, 00020F32h) Toledo, 2x 1 MB L2, 2.6 GHz, x13, 110 W

First stepping:
ACB2E (X2 Toledo) 0536, FX-60

Desktop A64 X2 939 (90 nm SOI DSL) Toledo
3800+: ADA3800DAA5CD 1.35/1.4V (JH E6 rev, 00020F32h) Toledo, 2x512 KB L2, 2.0 GHz, x10, 89 W (512 KB L2 per core "disabled")
4400+: ADA4400DAA6CD 1.35/1.4V (JH E6 rev, 00020F32h) Toledo, 2x1 MB L2, 2.2 GHz, x11, 110 W
4800+: ADA4800DAA6CD 1.35/1.4V (JH E6 rev, 00020F32h) Toledo, 2x1 MB L2, 2.4 GHz, x12, 110 W
FX-60: ADAFX60DAA6CD 1.35/1.4V (JH E6 rev, 00020F32h) Toledo, 2x1 MB L2, 2.6 GHz, x13, 110 W

165: OSA165DAA6CD 1.35/1.4V (JH E6 rev, 00020F32h) Toledo (Denmark), 2x1 MB L2, 1.8 GHz, x9, 110 W
170: OSA170DAA6CD 1.35/1.4V (JH E6 rev, 00020F32h) Toledo (Denmark), 2x1 MB L2, 2.0 GHz, x10, 110 W
175: OSA175DAA6CD 1.35/1.4V (JH E6 rev, 00020F32h) Toledo (Denmark), 2x1 MB L2, 2.2 GHz, x11, 110 W

Some review articles on the FX-60:
http://www.bit-tech.net/hardware/2006/01/10/amd_athlon_64_fx-60/1.html
http://www.pcstats.com/articleview.cfm?articleID=1918


A64 940, 754, 939 CPU Models, OPN code, rating (post 5)
Revisions and steppings (under construction) (post 6)

 

[hitechjb1]

(under construction)

The 940-pin socket AM2 rev. F CPU and DDR2

AMD AM2: More than just a Memory Change

Q3'05 AMD Roadmap; DDR2 and New Sockets for AMD

Intel Q3'05 Roadmap: Conroe Appears, Speculation Ensues


What are the key differences between DDR and DDR2

The upcoming AM2 will incorporate DDR2 memory modules.

The key differences between DDR and DDR2 are:

package (pin count) ...... TSOP/FPGA (184) .. FPGA (240)
frequency ................ 100/133/167/200 .. 100/133/167/200
data rate ................ 200/266/333/400 .. 400/533/667/800
voltage and power ........ 2.5V (nom) ....... 1.8V (nom) (lower power for DDR2)
DRAM chip density ........ 128 Mb - 1 Gb .... 256 Mb - 2 Gb
internal bank ............ 4 ................ 4/8
prefetch cycle ........... 2 ................ 4
CAS latency .............. 2/2.5/3 .......... 3/4/5
read latency ............. CAS .............. CAS+AL (AL = 0/1/2/3/4)
write latency ............ 1 ................ read_latency - 1
I/O width ................ x4/x8 ............ x4/x8/x16
signaling, termination ... none ............. selectable (better signal integrity for DDR2)
burst length ............. 2/4/8 ............ 4/8
...

(for refernece only, actual spec may differ)

Besides considering the common performance metric of latency and bandwidth, the above factors have to be considered as a whole and they have implications on future system scalability and overall system performance.


Memory frequency and latency tradeoff (post 195)

 

[hitechjb1]

Desktop A64 X2 AM2 940 (90 nm SOI DSL) Windsor (UNDER CONSTRUCTION)

FX-62: ADAFX62IAA6CS 1.30/1.35V (JH F2 rev, 00020F32h) Windsor, 2x1 MB L2, 2.8 GHz, x14, 125 W
5200+: ADA5200IAA6CS 1.30/1.35V (JH F2 rev, 00020F32h) Windsor, 2x1 MB L2, 2.6 GHz, x13, 89 W
4800+: ADA4800IAA6CS 1.30/1.35V (JH F2 rev, 00020F32h) Windsor, 2x1 MB L2, 2.4 GHz, x12, 65 W
4400+: ADA4400IAA6CS 1.30/1.35V (JH F2 rev, 00020F32h) Windsor, 2x1 MB L2, 2.2 GHz, x11, 65 W
4000+: ADA4000IAA6CS 1.30/1.35V (JH F2 rev, 00020F32h) Windsor, 2x1 MB L2, 2.0 GHz, x10, 65 W

5000+: ADA5000IAA5CU 1.30/1.35V (BH F2 rev, 00020FB2h) Windsor, 2x512 KB L2, 2.6 GHz, x13, 89 W
4600+: ADA4600IAA5CU 1.30/1.35V (BH F2 rev, 00020FB2h) Windsor, 2x512 KB L2, 2.4 GHz, x12, 65 W
4200+: ADA4200IAA5CU 1.30/1.35V (BH F2 rev, 00020FB2h) Windsor, 2x512 KB L2, 2.2 GHz, x11, 65 W
3800+: ADA3800IAA5CU 1.30/1.35V (BH F2 rev, 00020FB2h) Windsor, 2x512 KB L2, 2.0 GHz, x10, 65 W

CS = 00020F32h, Windsor AM2 940, rev. JH F2, 90 nm SOI DSL (2x1 MB L2)
CU = 00020FB2h, Windsor AM2 940, rev. BH F2, 90 nm SOI DSL (2x512 KB L2)


Windsor AM2 940 X2 3800+/4200+/4600+/5000+
rating = 2000/2200/2400/2600 MHz, 1.30/1.35V, 65/89 W, (Tcase 55-63 C)
90 nm SOI (DSL), 154 millions transistors, 183 (?) mm^2, 2x512 KB L2

Windsor AM2 940 X2 4000+/4400+/4800+/FX-62
rating = 2000/2200/2400/2800 MHz, 1.30/1.35V, 65/125 W, (Tcase 55-63 C)
90 nm SOI (DSL), 227 millions transistors, 230 (?) mm^2, 2x1M KB L2


940, 754, 939, AM2 940 CPU models and specifications (post 5)

How to identify the physical core of an A64 (post 86)

 

[David]

Unstuck due to age - we're on to a whole new range of chips...