# The Cache/CPU Connection

To figure the Mhz equivalent for the cache, use the formula

((1000/ns speed of cache) X 2)

You multiply by 2 because the PII cache runs at half the speed of the processor. Now there seems to be a little leeway on cache speed; it seems you can run cache pretty stably about 15% faster than its rating. So we’ll modify our formula to build that in, and we come up with

(((1000/ns) X 2) X 1.15)

This roughly establishes the maximum point at which most CPUs will run. Go faster than that, and your success rates suddenly drop.

Let’s apply this rough and ready formula to the various PII situations and see if they work:

The Klameths (233, 266, 300) all came with 7ns cache. (I think it really was 6.67ns cache, since I doubt Intel deliberately O/Cd the cache on the 300.) So, taking 6.67 as our figure, and applying our formula, we get

(((1000/6.67) X 2) X 1.15)= 345Mhz

This
accords pretty well with the O/Cing record of the Klameth: 333 was fairly easy, fewer got to 350, very few claimed more than that. Since the 233 and 300 had the same cache, which was much quicker than needed for 233Mhz but about what was needed for 300; that explains why the 233 was a good overclocking chip, and the 300 was not.

Moving on to the Deschutes:

The 333 and 350 both initially had the same 5.5ns cache. Using our little formula, we come with a maximum speed of (((1000/5.5) X 2) X 1.15)= 414Mhz. This accords very well with the O/C potential of the 333; where 400/412 was no big deal, but 448/450 was pretty difficult. Although the 350 had a limited O/Cing history mostly due to the
limited clock multiplier (briefly breached by the Abit BH6 SEL 100/66 switch); they pretty much came in the same way: 400/412 easily, 450 not so easily.

The 400 was given 5ns cache. Use the formula, and you come up with (((1000/5) X 2) X 1.15)= 460Mhz, which again, accords well with the 400s O/Cing record: 448 easily, not usually more than that.

The 450 was at 4.5ns cache; you know the routine (((1000/4.5) X 2) X 1.15)= 511Mhz. The 450 reaches 504 quite often, doesn’t reach 558 too often.

I’ll go back to the SL2W8s and kin in a moment; the CeleronAs work sort of the same way. Looks like Intel designed the cache to run as fast as the quickest member of the family. Here, you have to extrapolate numbers, the CeleronA has been announced to run as high as 400 Mhz. At 400Mhz, you would need 2.5ns cache to keep up with the CPU (1000ns/400Mhz). Since the cache is running at the speed of
the CPU; no need to multiply by 2, however, the 15% rule still seems to hold, so our CeleronA (and presumably Coppermine) formula simplifies to (1000/cache speed X 1.15). For the CeleronA, the formula goes (1000/2.5 X 1.15)= 460Mhz. Again, this fits in
well: the CeleronA usually does 450; it doesn’t usually do 500.

The SL2W8 and kin get a little more complicated. We have no less than four types of cache having been used here: 4.5ns, “225” 5ns, and 5.5ns cache. According to our formula, the 4.5ns should usually reach 504, the 5ns should reach 450 and the 5.5ns should have problems with 450, and that seems to be more or less true. However, you are getting reports of chips that seem to be doing better than they “should.” Since there seems to have been as many as 15-20% of chips in earlier families that have done the same; these may be “lucky cache chips” or perhaps something else is awry, including possibly this formula. Unfortunately, I doubt you are going to find a whole lot of people willing to open up their chips to verify speeds and software verificaton seems faulty.

I also wonder if these “225” aren’t really 4.5ns cache chips also. Since Intel is not likely to explain this all to us, we are left with inferring based on the data accumulated by folks such as Joe at overclockers.com and Andy Drake of the Unofficial Abit BX6/BH6 page,
from whose compilations I got most of the data to create this formula.

For the newer chips, Intel seems to be depending on a combination of cache speed and multiplier lock to limit overclocking, so giving a PII 333 5ns cache doesn’t terribly matter at a 5X locked multiple, since you are unlikely to get to 500 with it. The same applies to the CeleronA 333 and will to the 366; we know the success rate is low for
the 333 and I would venture it will be practically non-existent for the 366 (outside of 5.5X83). Keep something in mind, though. Intel doesn’t have to make something impossible, just very difficult. Sure, you can get some 333s to run at 500, but if you have a 20% success rate, that means a 80% failure rate, and that discourages overclockers very quickly.

We shouldn’t be looking at only the what, though. Why does Intel, which is supposed to be really against overclocking, creating chips that overclock so much, and what does that mean for the future?

For the PIIs, it looks like manufacturing convenience and cost savings are the reasons why we see what we see. The Deschutes 266s and 300s exist because it was easier and cheaper to make those chips and mark them down for a few months than to keep Klameth facilities operating (and not retooling for future chips).

It’s easier and often cheaper to standardize on one type of memory cache. If you are running a fab plant and your salary and bonus are contingent on how much money you make, you really don’t care what the marketing people in the head office think about overclockable chips if fixing it is going to cost you. If those folks raise enough of a
stink, you may change procedures for a bit just to get the head office off your back, but when the heat is off, you’ll go back to doing what benefits you the most. Or it could just be mopping up some excess inventory in slower cache chips. But the manufacturing people probably tell themselves that the vast majority of these chips will
always be run at their rated speeds, and if it gives a few enthusiasts an early Christmas; well, they weren’t going to be buying 450s anyway, and the window of opportunity isn’t going to be open very long.

Why the CeleronAs and Coppermines are different:

We have a different situation with the CeleronAs and the Coppermines. Cache is no longer a matter of slapping on what cache chips are handy, it has to be designed into the chip. Now it is very expensive indeed to keep redesigning cache to run faster and faster, so the Intel engineers don’t. They design the thing once to run as fast as it is ever going to run. That’s what they did with the CeleronAs, and since there seems to be even more reason to do so with the Coppermines (to compete with the K7, Intel’s going to have to ramp up the Mhz a lot faster than they are with the Celeron); I would expect to see the same.

Since this could cause problems with remarking down the road, though, Intel could end up putting some additional blocks beyond what they already have. The Coppermine weren’t initially supposed to have on-die cache; if they hadn’t, then it would have been easy to restrict O/Cing through the use of cache speeds. It is only
because Intel has to have very fast on-die cache for the Coppermine or otherwise face huge additional design and refitting costs that additional restrictions may be imposed. We’ll see. If they don’t, don’t be shocked to hear about folks running 700 or even 800Mhz Coppermines next summer or fall.

Overclockers received the following from Lasse S. of Norway:

“This might be old news to you guys but I’m telling you anyway…
I read your article where you stated that the 225MHz marking from Intel probably means the same as 4.5ns cache, and you’re right. You can easily translate the MHz rating to seconds by the formula Time=1/frequency (or Frequency=1/Time the other way) if you use this formula on the 225MHz cache rating from Intel you get:

Time=1/225.000.000=0.000000004444s= 4.44ns (very close to 4.5ns)

Now I understand why my SL2W8 won’t go higher than 464MHz…”