First, thanks to www.overclockers.com.tw for writing about this, Lonnie Chang for telling us about it, and Martin J. Hsu for some extra help.
Second, what I’m going to say today is not etched in stone. It’s
possible that this is not the way things are going to be, but we have to think that is the way it could be.
- Celeron engineering samples have been seen in Taiwan.
- Yes, they have SSE.
- They look to be Coppermines with half the cache disabled.
- No reports yet on overclockability.
- It could be possible, probably likely, that ALL Celerons will
be this way.
- If that is so, it does NOT mean all, most, or even many
Celerons will be Coppermine rejects.
- It is likely, though, that a larger percentage of Celerons will not
overclock much than we have seen in the past.
This is a different situation than we had with the PIIs/Celerons. The PIIs were much different chips than the Celerys. The Celerys
has ondie cache, the PIIs didn’t. Now, the Coppermines and Celerons
both have ondie cache on a chip that doesn’t take up much space.
It doesn’t really cost Intel “more” to use extra sand to build 256K of cache as opposed to 128K. However, it certainly would cost Intel more to build and run two factory lines instead of one. Having two factory lines instead of one also means Intel is less flexible in meeting demand. If it has one Coppermine and one Celeron machine, it can’t make both machines make Coppermines or Celerons.
However, if you make both Coppermines and Celerons from the same type
machine, you can use both types of machines to make either Coppermines or Celerons depending on the demand. This saves Intel a lot more money than some extra sand.
So what is the difference between a Coppermine and a Celeron?
Apparently, based on the article in www.overclockers.com.tw, a Celeron just has half the cache disabled via a control line. I don’t exactly know how they disable it, but let’s assume they cut a circuit line.
So what the engineering samples in Taiwan appear to be is a circumcised (or perhaps vasectomized) Celeron.
Wouldn’t this be hard for Intel to do? Not at all. All Intel needs is some robo-rabbi to cut the control line and circumcize Coppermines into Celerons. That shouldn’t be a big deal at all. If Intel needs more Coppermines, they just give Robo-Rabbi a break. If they need more Celerons? Put him on overtime.
Let me tell you how it could be good, and how it could be bad.
We may find out that we can reverse the circumcision one way or another, and you’ll end up with a Coppermine for a Celeron price.
I don’t think you need to worry that every Celeron is going to be a
lousy Coppermine, just because Intel will make a lot more Celerons than they will Coppermines.
What you should be worried about is:
- Intel has a lot of lousy Coppermines lying around from their
production the last couple months.
- Down the road, when Intel isn’t making 500 or 550 or 600E chips,
that those chips which don’t make the Coppermine cut will get sent to
Robo-Rabbi rather than be thrown out.
I don’t think the first will be that much of a problem, simply because Intel is selling Coppermines down to 500Mhz right now, and the Celerons will not go below that speed. You might get some chips rejected because half the cache was bad, but that shouldn’t be any big deal (unless reverse circumcision is possible).
I think the problem will emerge down the road when Intel is NOT selling the low speed Coppermines anymore. If Intel gets chips that function at Celeron but not Coppermine speeds, then I’d expect those chips will pay the rabbi a visit.
How many? Who knows? I don’t think all or more Celerons will end up
unoverclockable, just more than we’ve been used to. It may turn out to not be that big a deal, or that more cooling/higher voltage can coax Copp cuts into overclocking, but this could be a problem.
Again, this is based on some engineering samples. We may find out that what I’ve said isn’t so, but what I’ve said would make a lot of sense for Intel.